LAN9311-NU SMSC, LAN9311-NU Datasheet - Page 65

• Manufacturer Part Number: LAN9311-NU
• Description: IC ETHER SW 2PRT 16BIT 128-VTQFP
• Manufacturer: SMSC
• Type: Two Port Managed Ethernet Switchr

Specifications of LAN9311-NU

• Controller Type: Ethernet Switch Controller
• Interface: Serial EEPROM
• Voltage - Supply: 3.3V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Product: Ethernet Switches
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 MB, 100 MB
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Maximum Operating Temperature: + 70 C
• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• For Use With: 638-1076 - EVALUATION BOARD LAN9311-NU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1075

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
The following procedure should be followed in order to add, delete, and modify the ALR entries:
1. Write the
2. Write the
3. Poll the Make Pending bit in the
4. Write the
The ALR contains a search engine that is used by the host to read the MAC Address Table. This
engine is accessed by using the
Engine ALR Read Data 0 Register
Register
Note: The entries read are not necessarily in the same order as they were learned or manually
The following procedure should be followed in order to read the ALR entries:
1. Write the
2. Write the
3. Poll the Valid and End of Table bits in the
4. If the Valid bit is set, then the entry is valid and the data from the
5. If the End of Table bit is set, then exit.
6. Write the
7. Write the
8. Go to step 3.
Note: Refer to
ALR Write Data 1 Register (SWE_ALR_WR_DAT_1)
bits.
Note:An entry can be deleted by setting the Valid and Static bits to 0.
Entry)
(SWE_ALR_CMD_STS)
First Entry Bit)
(SWE_ALR_RD_DAT_1)
0 Register (SWE_ALR_RD_DAT_0)
(SWE_ALR_RD_DAT_1)
Next Entry bit)
added.
definitions of these registers.
(SWE_ALR_RD_DAT_1).
Switch Engine ALR Command Register (SWE_ALR_CMD)
Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0)
Switch Engine ALR Command Register (SWE_ALR_CMD)
Switch Engine ALR Command Register (SWE_ALR_CMD)
Switch Engine ALR Command Register (SWE_ALR_CMD)
Switch Engine ALR Command Register (SWE_ALR_CMD)
Switch Engine ALR Command Register (SWE_ALR_CMD)
Section 14.5.3.1, on page 368
until it is cleared.
until either are set.
can be stored.
Switch Engine ALR Command Register
DATASHEET
(SWE_ALR_RD_DAT_0), and
65
and
Switch Engine ALR Command Status Register
through
Switch Engine ALR Read Data 1 Register
Switch Engine ALR Read Data 1 Register
Section 14.5.3.6, on page 375
with the desired MAC address and control
Switch Engine ALR Read Data 1
Switch Engine ALR Read Data
with 0001h (Get Next Entry).
with 0000h.
with 0002h (Get First Entry).
with 0000h (Clear the Get
with 0000h (Clear the Get
register with 0004h (Make
(SWE_ALR_CMD),
Revision 1.7 (06-29-10)
and
Switch Engine
for detailed
Switch