SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 111

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

SAB 82532/SAF 82532
Operational Description
9.3.2.2 DMA Mode
If the RFIFO contains 32 bytes, the ESCC2 autonomously requests a block data transfer
by DMA by activating the DRR line for as long as the start of the 32
nd
(byte access) or
16
th
(word access) read cycle. This forces the DMA controller to continuously perform
bus cycles till 32 bytes are transferred from the ESCC2 to the system memory. If the
RFIFO contains less than 32 bytes, the ESCC2 requests the correct amount of transfer
cycles depending on the contents of the RFIFO and taking into account the selected bus
width.
Note: All available status information for each frame/data block after the end conditions
(RME or TCD) and for each character is the same as described above.
After the DMA controller has been set up for the reception of the next frame, the CPU
must issue a RMC command to acknowledge the completion of received data
processing. The ESCC2 will not initiate further DMA cycles by activating the DRR line
prior to the reception of RMC.
In HDLC/SDLC mode the RECEIVE STATUS REGISTER is automatically read from the
RFIFO with the last DMA-READ cycle of the received frame.
The status information after a RME interrupt is the same as in the interrupt driven mode.
The following figure gives an example of a DMA controlled reception sequence,
supposing that a ‘long’ frame (66 bytes) followed by two short frames (6 bytes each) is
received.
Figure 50
DMA Driven Reception Sequence Example (HDLC)
Semiconductor Group
111
07.96