SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 59

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Reception of Frames
The reception of frames functions similarly to the LAPB/LAPD operation (see
chapter 5.2.1).
Transmission of Frames
The ESCC2 does not transmit S-, or I-frames if not instructed to do so by the primary
station via an S-, or I-frame with the poll bit set.
The ESCC2 can be prepared to send an I-frame by the CPU by issuing an XIF command
(via CMDR) at any time. The transmission of the frame, however, will not be initiated by
the ESCC2 until reception of either an
• RR, or
• I-frame
with a poll bit set (p = ‘1’).
After the frame has been transmitted (with the final bit set), the XFIFO is inhibited and
the ESCC2 waits for the arrival of a positive acknowledgement.
Since the on-chip timer of the ESCC2 must be operated in the external mode
(a secondary may not poll the primary for acknowledgements), timer supervision must
be done by the primary station.
Upon the arrival of an acknowledgement the XFIFO is enabled and an interrupt is
forwarded to the CPU, either the
– message has been positively acknowledged (ALLS interrupt), or the
– message must be repeated (XMR interrupt).
Additionally, the timer can be used under CPU control to provide timer recovery of the
secondary if no acknowledgements are received at all.
Note: The transmission of transparent frames is only possible if the permission to send
Semiconductor Group
is given by an S-frame (p = ‘1’) or I-frame.
59
SAB 82532/SAF 82532
HDLC/SDLC Serial Mode
07.96

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