SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 81

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

The transmit clock pins (TxCLK) may also output clock signals in certain clock modes if
enabled via CCR2:TOE.
The clocking source for the DPLL’s is always the internal BRG; the scaling factor
(divider) of the BRG can be programmed through CCR2 and BGR registers between 1,
2, 4, 6 … 2048.
The ESCC2’s system clock is always derived from the transmit clock or from the master
clock (if master clock mode is enabled).
Master Clock Capabilities
A new clock source can be defined as master clock to allow full functionality of the
microprocessor interface (access to all status and control registers and FIFOs, DMA and
interrupt support) independent from the receive and transmit clocks. This new function
(enabled via bit CCR0:MCE) is useful for modem applications where continuous
generation of the receive and especially of the transmit clock cannot be guaranteed. The
master clock has to be supplied via pin XTAL1 (or a crystal connected to XTAL1 and 2).
Depending on the version, the maximum clock rate is 10 MHz (SAB/SAF 82532 N-10
and SAB/SAF 82532 H-10) or 2 MHz (SAB 82532 N and SAB 82532 H).
Note 1: The master clock is applicable to all clock modes except clock mode 5. For
Note 2: If bus configuration is selected in HDLC/SDLC mode (CCR0:SC2 … 0), the
Note 3: In SDLC loop mode the master clock option is not available.
Note 4: The conditions for the ratio between transmit clock, master clock and receive
Note 5: The internal timers run with the master clock.
Note 6: The serial interface (transmitter and receiver) are not sequenced by the master
Clock Mode 0 (external clocks)
Separate, externally generated receive and transmit clocks are supplied to the ESCC2
via their respective pins. The transmit clock can be directly supplied by pin TxCLK (mode
0a) or generated by the internal baud rate generator from the clock supplied by pin
XTAL1 (mode 0b). In the latter case, the transmit clock can be output via pin TxCLK.
Semiconductor Group
details refer to table 5.
‘One’-Insertion (CCR1:OIN) cannot be used in conjunction with the master
clock feature.
clock frequencies must be fulfilled to guarantee correct function (refer to the
notes of table 5).
clock however the FIFOs, DMA-UNIT and TIMER are.
81
Serial Interface (layer-1 functions)
SAB 82532/SAF 82532
07.96