SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 130

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

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Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Semiconductor Group
Receive Address Byte Low Register 1 (RAL1)
Access: read/write
The general function (WRITE or READ) and the meaning or contents of this register
depend on the selected operating mode:
• Auto- / Non-Auto-Mode (16-bit address) – WRITE Access only
• Auto- / Non-Auto-Mode (8-bit address) – WRITE Access only
• Transparent Mode 1 (high byte address recognition) – READ Access only
• Transparent Mode 0 (no address recognition) – READ Access only
• Extended Transparent Modes 0, 1 – READ Access only
In versions 2 and upwards, this register can be masked by setting the corresponding bits
in the mask register AML to allow extended broadcast address recognition. This feature
is applicable to all operating modes with address recognition.
(Read access not specified)
RAL1 can be programmed with the value of the first individual low address byte.
(Read access not specified)
According to X.25 LAPB protocol, the address in RAL1 is considered as the address
of a COMMAND frame.
(Write access has no influence)
RAL1 contains the byte following the high byte of the address in the receive frame (i.e.
the second byte after the opening flag).
(Write access has no influence)
RAL1 contains the first byte after the opening flag (first byte of received frame).
(Write access has no influence)
RAL1 contains the current data byte assembled from the RxD pin, the HDLC receiver
is bypassed (fully transparent reception without HDLC framing).
RAL1
7
address: ch-A: 28
ch-B: 68
130
H
H
RAL1
Detailed Register Description
SAB 82532/SAF 82532
HDLC Mode
07.96
0

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