SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 117

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Command Register (CMDR)
Access: write
Value after RESET: 00
RMC …
RHR …
RNR/XREP …
STI …
Semiconductor Group
CMDR
RMC
7
Receive Message Complete
Confirmation from CPU to ESCC2 that the current frame or data
block has been fetched following an RPF or RME interrupt, thus
the occupied space in the RFIFO can be released.
Note: In DMA Mode, this command has to be issued after an RME
Reset HDLC Receiver
All data in the RFIFO and the HDLC receiver is deleted. In
auto-mode, additionally the transmit and receive sequence
number counters are reset.
Receiver Not Ready/Transmission Repeat
The function of this command depends on the selected operation
mode (MDS1, MDS0, ADM bit in MODE):
• auto mode: RNR
• extended transparent mode 0, 1: XREP
Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after
H
Determines the status of the ESCC2 receiver, i.e. whether a
received frame is acknowledged via an RR or RNR supervisory
frame in auto-mode.
0 … Receiver Ready (RR)
1 … Receiver Not Ready (RNR)
If XREP is set to one together with XTF and XME (write 2A
to CMDR), the ESCC2 repeatedly transmits the contents of
the XFIFO
transparently, i.e. without FLAG, CRC or Bit Stuffing.
The cyclic transmission is stopped with an XRES command.
RHR
interrupt, to enable the generation of further receiver DMA
requests.
start.
address: ch-A: 20
XREP
RNR/
(1 … 32 bytes)
ch-B: 60
117
STI
H
H
XTF
without
Detailed Register Description
SAB 82532/SAF 82532
XIF
HDLC
XME
framing
HDLC Mode
XRES
07.96
0
fully
H

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