SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 139

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Channel Configuration Register 3 (CCR3)
Access: read/write
Value after RESET: 00
PRE1 … PRE0 …
EPT …
RADD …
CRL …
Semiconductor Group
CCR3
PRE1
7
Number of Preamble Repetition
If preamble transmission is initiated, the preamble defined via
register PRE is transmitted
00 … 1 times
01 … 2 times
10 … 4 times
11 … 8 times.
Enable Preamble Transmission
This bit enables transmission of a preamble. The preamble is
started after Interframe Time-fill transmission has been stopped
and a new frame is to be transmitted. The preamble consists of an
8-bit pattern repeated a number of times. The pattern is defined
via register PRE, the number of repetitions is selected by bits
PRE0 and PRE1.
Note: The ‘Shared Flag’ feature is not influenced by preamble
Receive Address Pushed to RFIFO
If this bit is set to ‘1’, the received HDLC address information (1 or
2 bytes, depending on the address mode selected via
MODE:ADM) is pushed to RFIFO. This function is applicable in
auto mode, non-auto mode and transparent mode 1.
CRC Reset Level
This bit defines the initialization for the internal receive and
transmit CRC generators:
0 … Initialized to (FFFF)FFFF
1 … Initialized to (0000)0000
H
HDLC/SDLC applications.
PRE0
transmission. Zero Bit insertion is disabled during preamble
transmission.
address: ch-A: 2F
EPT
ch-B: 6F
139
RADD
H
H
H
.
CRL
Detailed Register Description
H
. Default value for most
SAB 82532/SAF 82532
RCRC XCRC
HDLC Mode
PSD
07.96
0

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