SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 205

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SAF82532N10V32A

Manufacturer Part Number
SAF82532N10V32A
Description
IC CONTROLLER 2-CH SER 68-PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAF82532N10V32A

Controller Type
Serial Communications Controller (SCC)
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
8mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
68-PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Other names
SAF82532N10V32A
SAF82532N10V32AIN

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAF82532N10V32A
Manufacturer:
Infineon Technologies
Quantity:
10 000
Command Register (CMDR)
Access: write
Value after RESET: 00
RMC …
RRES …
RFRD …
STI …
XF …
Semiconductor Group
CMDR
RMC
7
Receive Message Complete
Confirmation from CPU to ESCC2 that the current frame or data
block has been fetched following an RPF or RME interrupt, thus
the occupied space in the RFIFO can be released.
Note: In DMA Mode, this command has to be issued after an
Receiver Reset
All data in RFIFO and receiver is deleted. The receiver returns to
Hunt state.
Receive FIFO Read Enable
The CPU can have access to RFIFO by issuing the RFRD
command before threshold level or the end condition (TCD) are
fulfilled. After issuing the RFRD command the CPU has to wait for
TCD interrupt, before reading RBC and RFIFO. The number of
valid bytes is determined by reading the RBCL register.
Start Timer
The internal timer is started.
Note: The timer is stopped by rewriting the TIMR register after
Transmit Frame
• Interrupt Mode
• DMA Mode
H
After having written up to 32 bytes/16 words to the XFIFO, this
command initiates the transmission of data.
After having written the amount of data to be transmitted to the
XBCH, XBCL registers, this command initiates the data transfer
from system memory to ESCC2 by DMA. Serial data
transmission starts as soon as 32 bytes/16 words are stored in
the XFIFO or the Transmit Byte Counter value is reached.
RRES
TCD interrupt in order to enable the generation of further
receiver DMA requests.
start.
address: ch-A: 20
RFRD
ch-B: 60
205
STI
H
H
XF
Detailed Register Description
SAB 82532/SAF 82532
HUNT
XME
BISYNC Mode
XRES
07.96
0

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