SAF82532N10V32A Infineon Technologies, SAF82532N10V32A Datasheet - Page 118

• Manufacturer Part Number: SAF82532N10V32A
• Description: IC CONTROLLER 2-CH SER 68-PLCC
• Manufacturer: Infineon Technologies

Specifications of SAF82532N10V32A

• Controller Type: Serial Communications Controller (SCC)
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 8mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Other names: SAF82532N10V32A; SAF82532N10V32AIN

Semiconductor Group
XTF …
XIF …
XME …
XRES …
Transmit Transparent Frame
• Interrupt Mode
• DMA Mode
Transmit I-Frame (used in auto-mode only!)
Initiates the transmission of an I-frame in auto-mode. Additionally
to the opening flag sequence, the address and control field of the
frame is automatically added by ESCC2.
Transmit Message End (used in interrupt-mode only!)
Indicates that the data block written last to the transmit FIFO
completes the current frame. The ESCC2 can terminate the
transmission operation properly by appending the CRC and the
closing flag sequence to the data.
In DMA Mode, the end of the frame is determined by the Transmit
Byte Count in XBCH, XBCL, thus, XME is not used in this case.
Transmitter Reset
XFIFO is cleared of any data and an abort sequence (seven ‘1’s)
followed by interframe time-fill is transmitted. In response to
XRES an XPR interrupt is generated.
This command can be used by the CPU to abort a frame currently
in transmission.
Note: The maximum time between writing to the CMDR register
After having written up to 32 bytes to the XFIFO, this command
initiates the transmission of a transparent frame. An opening
flag sequence is automatically added to the data by the
ESCC2.
After having written the length of the frame to be transmitted to
the XBCH, XBCL registers, this command initiates the data
transfer from system memory to ESCC2 by DMA. Serial data
transmission starts as soon as 32 bytes are stored in the XFIFO
or the Transmit Byte Counter value is reached.
and the execution of the command is 2.5 clock cycles.
Therefore, if the CPU operates with a very high clock rate
in comparison with the ESCC2’s clock, it is recommended
to check the CEC bit of the STAR register before writing to
the CMDR register to avoid any loss of commands.
118
Detailed Register Description
SAB 82532/SAF 82532
HDLC Mode
07.96