PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 122

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

PIC16(L)F1826/27
REGISTER 12-3:
REGISTER 12-4:
REGISTER 12-5:
DS41391D-page 122
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-0
Note 1:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
bit 4-0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5
bit 4-0
Note 1:
R/W-1/1
R/W-x/x
TRISA7
R/W-x/u
LATA7
RA7
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.
Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O
pin values.
RA<7:0>: PORTA I/O Value bits
1 = Port pin is > V
0 = Port pin is < V
TRISA<7:6>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
TRISA5: RA5 Port Tri-State Control bit
This bit is always ‘1’ as RA5 is an input only
TRISA<4:0>: PORTA Tri-State Control bit
1 = PORTA pin configured as an input (tri-stated)
0 = PORTA pin configured as an output
LATA<7:6>: RA<7:6> Output Latch Value bits
Unimplemented: Read as ‘0
LATA<4:0>: RA<4:0> Output Latch Value bits
R/W-1/1
R/W-x/x
TRISA6
R/W-x/u
LATA6
RA6
PORTA: PORTA REGISTER
TRISA: PORTA TRI-STATE REGISTER
LATA: PORTA DATA LATCH REGISTER
W = Writable bit
‘0’ = Bit is cleared
W = Writable bit
‘0’ = Bit is cleared
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
x = Bit is unknown
x = Bit is unknown
IH
IL
TRISA5
R-1/1
R-x/x
RA5
U-0
—
(1)
R/W-1/1
R/W-x/u
R/W-x/x
TRISA4
LATA4
RA4
(1)
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-x/x
R/W-1/1
R/W-x/u
TRISA3
LATA3
RA3
R/W-1/1
R/W-x/u
R/W-x/x
TRISA2
LATA2
RA2
 2011 Microchip Technology Inc.
R/W-1/1
R/W-x/u
R/W-x/x
TRISA1
LATA1
RA1
R/W-1/1
R/W-x/x
TRISA0
R/W-x/u
LATA0
RA0
bit 0
bit 0
bit 0