PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 241

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

25.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
TABLE 25-1:
 2011 Microchip Technology Inc.
APFCON0
ANSELA
ANSELB
INTCON
PIE1
PIR1
SSPxBUF
SSPxCON1
SSPxCON3
SSPxSTAT
TRISA
TRISB
Legend:
Note 1:
Name
*
SPI OPERATION IN SLEEP MODE
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
PIC16(L)F1827 only.
Synchronous Serial Port Receive Buffer/Transmit Register
RXDTSEL
TMR1GIE
TMR1GIF
ACKTIM
TRISA7
TRISB7
ANSB7
WCOL
Bit 7
SMP
GIE
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
SDO1SEL
SSPxOV
TRISA6
TRISB6
ANSB6
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
—
SSPxEN
SS1SEL
TMR0IE
TRISA5
TRISB5
ANSB5
RCIE
RCIF
SCIE
Bit 5
D/A
—
P2BSEL
TRISA4
TRISB4
ANSA4
ANSB4
BOEN
INTE
TXIE
Bit 4
TXIF
CKP
P
(1)
CCP2SEL
SSPxM3
SSP1IE
SSP1IF
TRISA3
TRISB3
ANSA3
ANSB3
SDAHT
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
S
(1)
PIC16(L)F1826/27
SSPxM2
P1DSEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISB2
ANSA2
ANSB2
Bit 2
R/W
P1CSEL
SSPxM1
TMR2IE
TMR2IF
TRISA1
TRISB1
ANSA1
ANSB1
AHEN
Bit 1
INTF
UA
CCP1SEL
SSPxM0
TMR1IE
TMR1IF
TRISA0
TRISB0
ANSA0
DHEN
IOCIF
Bit 0
DS41391D-page 241
BF
—
Register
on Page
235*
123
128
280
282
279
122
127
119
86
87
91