PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 155

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

17.4
In order for the DAC module to consume the least
amount of power, one of the two voltage reference input
sources to the resistor ladder must be disconnected.
Either the positive voltage source, (V
negative voltage source, (V
The negative voltage source is disabled by setting the
DACLPS bit in the DACCON0 register. Clearing the
DACLPS bit in the DACCON0 register disables the
positive voltage source.
17.4.1
The DAC output voltage can be set to V
the least amount of power consumption by performing
the following:
• Clearing the DACEN bit in the DACCON0 register.
• Setting the DACLPS bit in the DACCON0 register.
• Configuring the DACPSS bits to the proper
• Configuring the DACR<4:0> bits to ‘11111’ in the
FIGURE 17-3:
17.5
When the device wakes up from Sleep through an
interrupt or a Watchdog Timer time-out, the contents of
the DACCON0 register are not affected. To minimize
current consumption in Sleep mode, the voltage
reference should be disabled.
17.6
A device Reset affects the following:
• DAC is disabled.
• DAC output voltage is removed from the
• The DACR<4:0> range select bits are cleared.
 2011 Microchip Technology Inc.
positive source.
DACCON1 register.
DACOUT pin.
V
V
SOURCE
Output Clamped to Positive Voltage Source
SOURCE
DACEN = 0
DACLPS = 1
Low-Power Voltage State
Operation During Sleep
Effects of a Reset
OUTPUT CLAMPED TO POSITIVE
VOLTAGE SOURCE
+
-
OUTPUT VOLTAGE CLAMPING EXAMPLES
SOURCE
R
R
R
DACR<4:0> = 11111
DAC Voltage Ladder
(see
-) can be disabled.
SOURCE
Figure
SOURCE
+), or the
17-1)
+ with
This is also the method used to output the voltage level
from the FVR to an output pin. See
“Operation During Sleep”
Reference
17.4.2
The DAC output voltage can be set to V
the least amount of power consumption by performing
the following:
• Clearing the DACEN bit in the DACCON0 register.
• Clearing the DACLPS bit in the DACCON0 register.
• Configuring the DACNSS bits to the proper
• Configuring the DACR<4:0> bits to ‘00000’ in the
This allows the comparator to detect a zero-crossing
while not consuming additional current through the DAC
module.
Reference
V
V
Output Clamped to Negative Voltage Source
SOURCE
SOURCE
negative source.
DACCON1 register.
DACEN = 0
DACLPS = 0
PIC16(L)F1826/27
+
-
Figure 17-3
Figure 17-3
OUTPUT CLAMPED TO NEGATIVE
VOLTAGE SOURCE
for output clamping examples.
for output clamping examples.
R
R
R
for more information.
DACR<4:0> = 00000
DAC Voltage Ladder
(see
DS41391D-page 155
Figure
SOURCE
Section 17.5
17-1)
- with