PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 96

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

PIC16(L)F1826/27
9.1.1
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
FIGURE 9-1:
TABLE 9-1:
DS41391D-page 96
Name
INTCON
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIE4
PIR1
PIR2
PIR4
STATUS
WDTCON
Legend:
Note 1:
Instruction Flow
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
(INTCON reg.)
Note
Interrupt flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
cleared.
(1)
(1)
OSC1
1:
2:
3:
4:
PC
(1)
(2)
— = unimplemented, read as ‘0’. Shaded cells are not used in Power-down mode.
PIC16(L)F1827 only.
WAKE-UP USING INTERRUPTS
XT, HS or LP Oscillator mode assumed.
CLKOUT is not available in XT, HS, or LP Oscillator modes, but shown here for timing reference.
T
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TMR1GIE
TMR1GIF
OST
IOCBN7
IOCBP7
IOCBF7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
IOCBF6
IOCBN6
IOCBP6
PEIE
ADIE
ADIF
Bit 6
C2IE
C2IF
(drawing not to scale). This delay applies only to XT, HS or LP Oscillator modes.
—
—
—
—
Inst(PC + 1)
Sleep
PC + 1
WDTPS4
TMR0IE
IOCBN5
IOCBP5
IOCBF5
RCIE
RCIF
Bit 5
C1IE
C1IF
—
—
—
Processor in
Sleep
WDTPS3
IOCBN4
IOCBF4
IOCBP4
PC + 2
INTE
TXIE
EEIE
EEIF
Bit 4
TXIF
TO
—
—
T
OST (3)
WDTPS2
IOCBF3
IOCBN3
IOCBP3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
SSP1IE
BCL1IE
SSP1IF
BCL1IF
IOCIE
Bit 3
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
PD
—
—
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
PC + 2
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
cuted
WDTPS1
IOCBN2
IOCBP2
TMR0IF
IOCBF2
CCP1IE
CCP1IF
Bit 2
—
—
—
—
Z
(4)
Dummy Cycle
PC + 2
WDTPS0
IOCBN1
IOCBF1
IOCBP1
TMR2IE
TMR2IF
BCL2IE
BCL2IF
Bit 1
INTF
DC
—
—
 2011 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
CCP2IE
CCP2IF
SWDTEN
IOCBF0
IOCBN0
IOCBP0
TMR1IE
TMR1IF
SSP2IE
SSP2IF
IOCIF
Bit 0
C
(1)
(1)
Inst(0005h)
Inst(0004h)
Register on
0005h
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