PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 23

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

TABLE 3-3:
Legend:
00Bh
00Ch
00Dh
00Eh
01Ah
01Bh
01Ch
01Dh
01Eh
000h
00Fh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Fh
020h
06Fh
070h
07Fh
Note 1:
Core Registers
(Table
CPSCON0
CPSCON1
BANK 0
T1GCON
96 Bytes
General
Purpose
Register
PORTA
PORTB
TMR1H
T1CON
T2CON
PIR3
PIR4
TMR1L
TMR0
TMR2
PIR1
PIR2
Available only on PIC16(L)F1827.
PR2
—
—
—
—
= Unimplemented data memory locations, read as ‘0’
3-2)
(1)
(1)
PIC16(L)F1826/27 MEMORY MAP
08Bh
08Ch
08Dh
08Eh
09Ah
09Bh
09Ch
09Dh
09Eh
0A0h
0EFh
0FFh
080h
08Fh
090h
091h
092h
093h
094h
095h
096h
097h
098h
099h
09Fh
0F0h
Core Registers
OSCTUNE
(Table
OSCSTAT
WDTCON
70h – 7Fh
BANK 1
OSCCON
Accesses
ADRESL
ADRESH
ADCON0
ADCON1
OPTION
80 Bytes
General
Purpose
Register
PIE3
PIE4
TRISA
TRISB
PCON
PIE1
PIE2
—
—
—
—
3-2)
(1)
(1)
10Bh
10Ch
10Dh
10Eh
11Ah
11Bh
11Ch
11Dh
11Eh
100h
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Fh
120h
16Fh
170h
17Fh
Core Registers
CM1CON0
CM1CON1
CM2CON0
CM2CON1
DACCON0
DACCON1
(Table
APFCON0
APFCON1
BORCON
70h – 7Fh
BANK 2
FVRCON
Accesses
SRCON0
SRCON1
80 Bytes
CMOUT
General
Purpose
Register
LATA
LATB
—
—
—
—
—
3-2)
18Bh
18Ch
18Dh
18Eh
18Fh
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
1EFh
1F0h
1FFh
180h
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
Core Registers
BAUDCON
80 Bytes
(Table
70h – 7Fh
BANK 3
EEADRH
SPBRGH
Accesses
ANSELA
ANSELB
EEADRL
EEDATH
EECON1
EECON2
SPBRGL
EEDATL
Purpose
Register
RCREG
General
TXREG
RCSTA
TXSTA
—
—
—
—
—
3-2)
(1)
20Bh
20Ch
20Dh
20Eh
20Fh
21Ah
21Bh
21Ch
21Dh
21Eh
21Fh
26Fh
27Fh
200h
210h
211h
212h
213h
214h
215h
216h
217h
218h
219h
220h
270h
Unimplemented
Core Registers
SSP2MASK
SSP2CON2
SSP2CON3
SSP2STAT
SSP2CON
SSP2BUF
SSP2ADD
SSP1MASK
SSP1CON2
SSP1CON3
SSP1STAT
Read as ‘0’
48 Bytes
(Table
SSP1ADD
SSP1CON
SSP1BUF
70h – 7Fh
BANK 4
Accesses
Purpose
Register
General
WPUA
WPUB
—
—
—
—
3-2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
28Bh
28Ch
28Dh
28Eh
28Fh
292h
293h
294h
295h
29Ah
29Bh
29Ch
29Dh
29Eh
29Fh
2A0h
2EFh
2F0h
2FFh
280h
290h
291h
296h
297h
298h
299h
Unimplemented
Core Registers
PSTR2CON
PWM2CON
CCPTMRS
CCP2CON
PWM1CON
PSTR1CON
CCPR2H
Read as ‘0’
(Table
CCP1CON
CCPR2L
CCP2AS
70h – 7Fh
BANK 5
CCPR1H
Accesses
CCPR1L
CCP1AS
—
—
—
—
—
—
—
3-2)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
300h
30Bh
30Ch
30Dh
30Eh
30Fh
310h
311h
312h
313h
314h
315h
316h
317h
318h
319h
31Ah
31Bh
31Ch
31Dh
31Eh
31Fh
320h
36Fh
370h
37Fh
Unimplemented
Core Registers
CCP3CON
CCP4CON
CCPR3H
CCPR4H
Read as ‘0’
(Table
CCPR3L
CCPR4L
70h – 7Fh
BANK 6
Accesses
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3-2)
(1)
(1)
(1)
(1)
(1)
(1)
380h
38Bh
38Ch
38Dh
38Eh
38Fh
390h
391h
392h
393h
394h
395h
396h
397h
398h
399h
39Ah
39Bh
39Ch
39Dh
39Eh
39Fh
3A0h
3EFh
3F0h
3FFh
Unimplemented
Core Registers
Read as ‘0’
(Table
CLKRCON
MDCARH
70h – 7Fh
BANK 7
MDCARL
Accesses
MDCON
MDSRC
IOCBN
IOCBP
IOCBF
—
—
—
—
—
—
—
—
—
—
—
—
3-2)