PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 94

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

PIC16(L)F1826/27
8.6.9
The PIR4 register contains the interrupt flag bits, as
shown in
REGISTER 8-9:
TABLE 8-1:
DS41391D-page 94
INTCON
OPTION_REG
PIE1
PIE2
PIE3
PIE4
PIR1
PIR2
PIR3
PIR4
Legend:
Note 1:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-2
bit 1
bit 0
Note 1:
(1)
(1)
(1)
(1)
Name
U-0
—
Register
— = unimplemented locations read as ‘0’. Shaded cells are not used by Interrupts.
PIC16(L)F1827 only.
This register is only available on PIC16(L)F1827.
PIR4 REGISTER
Unimplemented: Read as ‘0’
BCL2IF: MSSP2 Bus Collision Interrupt Flag bit
1 = A Bus Collision was detected (must be cleared in software)
0 = No Bus collision was detected
SSP2IF: Master Synchronous Serial Port 2 (MSSP2) Interrupt Flag bit
1 = The Transmission/Reception/Bus Condition is complete (must be cleared in software)
0 = Waiting to Transmit/Receive/Bus Condition in progress
TMR1GIE
TMR1GIF
SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS
WPUEN
8-9.
OSFIE
OSFIF
Bit 7
GIE
—
—
—
—
U-0
—
PIR4: PERIPHERAL INTERRUPT REQUEST REGISTER 4
INTEDG
(1)
PEIE
ADIE
ADIF
Bit 6
C2IE
C2IF
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
—
—
—
U-0
—
TMR0CS
TMR0IE
CCP4IE
CCP4IF
RCIE
RCIF
Bit 5
C1IE
C1IF
—
—
U-0
—
TMR0SE
CCP3IE
CCP3IF
Bit 4
INTE
TXIE
EEIE
TXIF
EEIF
—
—
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
TMR6IE
TMR6IF
SSP1IE
BCL1IE
SSP1IF
BCL1IF
IOCIE
U-0
Bit 3
PSA
—
—
—
Note 1: The PIR4 register is available only on the
2: Interrupt flag bits are set when an inter-
TMR0IF
CCP1IE
CCP1IF
Bit 2
PS2
PIC16(L)F1827 device.
rupt condition occurs, regardless of the
state of its corresponding enable bit or
the Global Enable bit, GIE, of the
INTCON register. User software should
ensure the appropriate interrupt flag bits
are clear prior to enabling an interrupt.
—
—
—
—
—
—
U-0
—
TMR2IE
TMR4IE
TMR2IF
TMR4IF
BCL2IE
BCL2IF
Bit 1
INTF
PS1
 2011 Microchip Technology Inc.
—
—
(1)
R/W/HS-0/0
BCL2IF
CCP2IE
CCP2IF
TMR1IE
TMR1IF
SSP2IE
SSP2IF
IOCIF
Bit 0
PS0
—
—
(1)
(1)
R/W/HS-0/0
SSP2IF
Register
on Page
177
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90
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bit 0