PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 78

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

PIC16(L)F1826/27
7.10
Upon any Reset, multiple bits in the STATUS and
PCON register are updated to indicate the cause of the
Reset.
tions of these registers.
TABLE 7-3:
TABLE 7-4:
DS41391D-page 78
Power-on Reset
MCLR Reset during normal operation
MCLR Reset during Sleep
WDT Reset
WDT Wake-up from Sleep
Brown-out Reset
Interrupt Wake-up from Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on
STKOVF STKUNF RMCLR
0
0
0
0
u
u
u
u
u
u
1
u
2: If a Status bit is not implemented, that bit will be read as ‘0’.
Table 7-3
Determining the Cause of a Reset
the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.
0
0
0
0
u
u
u
u
u
u
u
1
and
RESET STATUS BITS AND THEIR SIGNIFICANCE
RESET CONDITION FOR SPECIAL REGISTERS
Table 7-4
Condition
1
1
1
1
u
u
u
0
0
u
u
u
show the Reset condi-
RI
1
1
1
1
u
u
u
u
u
0
u
u
POR
0
0
0
u
u
u
u
u
u
u
u
u
BOR
x
x
x
0
u
u
u
u
u
u
u
u
TO
1
0
x
1
0
0
1
u
1
u
u
u
Program
PC + 1
Counter
PC + 1
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
PD
1
x
0
1
u
0
0
u
0
u
u
u
(1)
Power-on Reset
Illegal, TO is set on POR
Illegal, PD is set on POR
Brown-out Reset
WDT Reset
WDT Wake-up from Sleep
Interrupt Wake-up from Sleep
MCLR Reset during normal operation
MCLR Reset during Sleep
RESET Instruction Executed
Stack Overflow Reset (STVREN = 1)
Stack Underflow Reset (STVREN = 1)
(2)
---1 1000
---u uuuu
---1 0uuu
---0 uuuu
---0 0uuu
---1 1uuu
---1 0uuu
---u uuuu
---u uuuu
---u uuuu
Register
STATUS
 2011 Microchip Technology Inc.
Condition
00-- 110x
uu-- 0uuu
uu-- 0uuu
uu-- uuuu
uu-- uuuu
00-- 11u0
uu-- uuuu
uu-- u0uu
1u-- uuuu
u1-- uuuu
Register
PCON