PIC16F1827-E/P Microchip Technology Inc., PIC16F1827-E/P Datasheet - Page 207

• Manufacturer Part Number: PIC16F1827-E/P
• Description: 7 KB Flash, 384 bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F1827-E/P

• A/d Inputs: 12-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 8 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 16
• Interface: CAN/I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 7K Bytes
• Ram Size: 384 Bytes
• Speed: 32 MHz
• Timers: 4-8-bit, 1-16-bit
• Voltage, Range: 1.8-5.5 V
• Standby Current (pic16lf182x): 30 nA @ 1.8 V, Typical

24.2.5
The Compare mode is dependent upon the system
clock (F
down during Sleep mode, the Compare mode will not
function properly during Sleep.
TABLE 24-4:
 2011 Microchip Technology Inc.
APFCON0
CCPxCON
CCPRxL
CCPRxH
CM1CON0
CM1CON1
CM2CON0
CM2CON1
INTCON
PIE1
PIE2
PIE3
PIR1
PIR2
PIR3
T1CON
T1GCON
TMR1L
TMR1H
TRISA
TRISB
Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1:
Name
(2)
(2)
2:
OSC
*
Page provides register information.
Applies to ECCP modules only.
PIC16(L)F1827 only.
COMPARE DURING SLEEP
) for proper operation. Since F
Capture/Compare/PWM Register x Low Byte (LSB)
Capture/Compare/PWM Register x High Byte (MSB)
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1CS1 TMR1CS0 T1CKPS1
RXDTSEL SDO1SEL
TMR1GIE
TMR1GIF
TMR1GE
PxM1
C1INTP
C2INTP
TRISA7
TRISB7
OSFIE
OSFIF
C1ON
C2ON
Bit 7
GIE
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
(1)
T1GPOL
C1INTN
C2INTN
PxM0
TRISA6
TRISB6
C1OUT
C2OUT
PEIE
ADIE
C2IE
ADIF
Bit 6
C2IF
—
—
(1)
C1PCH1
C2PCH1
SS1SEL
TMR0IE
CCP4IE
CCP4IF
TRISA5
TRISB5
T1GTM
DCxB1
C1OE
C2OE
RCIE
RCIF
C1IE
Bit 5
C1IF
OSC
P2BSEL
T1CKPS0
C1PCH0
C2PCH0
T1GSPM
is shut
CCP3IE
CCP3IF
TRISA4
TRISB4
C1POL
C2POL
DCxB0
INTE
EEIE
Bit 4
TXIE
TXIF
EEIF
(2)
T1GGO/DONE
CCP2SEL
T1OSCEN
CCPxM3
TMR6IE
TMR6IF
TRISA3
TRISB3
BCL1IE
SSPIE
SSPIF
IOCIE
BCLIF
Bit 3
24.2.6
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
registers, APFCON0 and APFCON1. To determine
which pins can be moved and what their default loca-
tions are upon a reset, see
Pin Function”
—
—
—
—
(2)
PIC16(L)F1826/27
CCPxM2
P1DSEL
T1SYNC
T1GVAL
TMR0IF
CCP1IE
CCP1IF
TRISA2
TRISB2
C1SP
C2SP
ALTERNATE PIN LOCATIONS
Bit 2
—
—
—
—
—
—
for more information.
CCPxM1
C1NCH1
C2NCH1
P1CSEL
T1GSS1
TMR2IE
TMR4IE
TMR2IF
TMR4IF
TRISA1
TRISB1
C1HYS
C2HYS
INTF
Bit 1
—
—
—
Section 12.1 “Alternate
CCP1SEL
CCP2IE
CCP2IF
TMR1ON
C1SYNC
C2SYNC
CCPxM0
C1NCH0
C2NCH0
T1GSS0
TMR1IE
TMR1IF
TRISA0
TRISB0
IOCIF
Bit 0
DS41391D-page 207
—
—
(2)
(2)
Register
on Page
204*
204*
177*
177*
226
170
171
170
171
185
186
122
127
119
86
87
88
89
91
92
93