ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet
ADV202-SD-EB
Specifications of ADV202-SD-EB
ADV202-SD-EB Summary of contents
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... ITU.R-BT1358 (625p) or any video format with a maximum input rate of 65 MSPS for irreversible mode or 40 MSPS for reversible mode Two or more ADV202s can be combined to support full- frame SMPTE274M HDTV (1080i) or SMPTE296M (720p) Interlaces temporally coherent frame-based SD video sources for improved performance ...
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... Pin Function Descriptions ........................................................ 22 Theory of Operation ...................................................................... 25 Wavelet Engine ........................................................................... 25 Entropy Codecs........................................................................... 25 Embedded Processor System .................................................... 25 Memory System .......................................................................... 25 Internal DMA Engine ................................................................ 25 ADV202 Interface........................................................................... 26 REVISION HISTORY 1/05—Rev Rev. B Updated Outline Dimensions ....................................................... 39 Video Interface (VDATA Bus).................................................. 26 Host Interface (HDATA Bus) ................................................... 26 Direct and Indirect Registers .................................................... 26 Control Access Registers ........................................................... 27 Pin Configuration and Bus Sizes/Modes ...
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... GENERAL DESCRIPTION (continued from Page 1) The ADV202 can process images at a rate of 40 MSPS in reversible mode and at higher rates when used in irreversible mode. The ADV202 contains a dedicated wavelet transform engine, three entropy codecs, an on-board memory system, and an embedded RISC processor that can provide a complete JPEG2000 compression/decompression solution ...
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... Dynamic Current, Core (JCLK Frequency = 150 MHz) Dynamic Current, Core (JCLK Frequency = 108 MHz) Dynamic Current, Core (JCLK Frequency = 81 MHz) Dynamic Current, I/O Dynamic Current, PLL 1 No clock or I/O activity. 2 ADV202-150 only. INPUT/OUTPUT SPECIFICATIONS Table 2. Parameter Description V High Level Input Voltage IH (3.3 V) ...
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... VCLK Width Low VCLKL t VCLK Width High VCLKH t RESET Width Low RST 1 For a definition of MCLK, see the PLL section. MCLK VCLK t MCLK t t MCLKL MCLKH t VCLK t t VCLKL VCLKH Figure 2. Input Clock Rev Page ADV202 Min Typ Max Unit 13.3 100 13 MCLK cycles 1 ...
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... ADV202 NORMAL HOST MODE—READ OPERATION Table 4. Parameter Description t [dir ACK, Direct Registers and FIFO Accesses ACK t [indir ACK, Indirect Registers ACK t [dir] Read Access Time, Direct Registers DRD t [indir] Read Access Time, Indirect Registers DRD t Data Hold HZRD Setup SC t Address Setup ...
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... Write Cycle Time WCYC 1 For a definition of JCLK, see the PLL section ADDR ACK HDATA WCYC ACK VALID Figure 4. Normal Host Mode—Write Operation Rev Page Min Typ Max 5 1.5 × JCLK + 7 2.5 × JCLK + 7.0 ns 3.0 1 2.5 2.5 5 ADV202 Unit JCLK JCLK JCLK ...
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... ADV202 DREQ / DACK DMA MODE—SINGLE FIFO WRITE OPERATION Table 6. Parameter Description 1 DREQ DREQ Pulse Width PULSE t DACK Assert to Subsequent DREQ Delay DREQ DACK Setup WE SU Data to DACK Deassert Setup t SU Data to DACK Deassert Hold t HD DACK DACK Assert Pulse Width ...
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... WESU WEFB HDATA 0 Figure 7. Fly-By DMA Mode —Single Write Cycle ( DREQ Pulse Width Is Programmable) FSC0 WE FIFO NOT FULL FSRQ0 HDATA 0 Figure 8. DCS DMA Mode—Single Write Access (Rev. 0.1 and Higher WFSRQ 1 Rev Page ADV202 t WEHD FIFO FULL 2 NOT WRITTEN TO FIFO ...
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... ADV202 DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION Table 7. Parameter Description 1 DREQ DREQ Pulse Width PULSE t DACK Assert to Subsequent DREQ Delay DREQ DACK Setup DACK to Data Valid RD t Data Hold HD DACK DACK Assert Pulse Width LO DACK DACK Deassert Pulse Width Hold after DACK Deassert ...
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... DACK DACK LO DACK t RDSU RDFB HDATA Figure 11. Fly-By DMA Mode—Single Read Cycle ( DREQ Pulse Width Is Programmable) FCS0 RD FIFO NOT EMPTY FSRQ0 0 HDATA Figure 12. DCS DMA Mode—Single Read Access (Rev. 0.1 and Higher RDFSRQ FIFO EMPTY 1 Rev Page ADV202 t RDHD ...
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... ADV202 EXTERNAL DMA MODE—FIFO WRITE, BURST MODE Table 8. Parameter Desription 1 DREQ DREQ Pulse Width PULSE t DACK to DREQ Deassert (DR × Pulse = 0) DREQ RTN t DACK to WE Setup DACK SU t Data Setup SU t Data Hold Assert Pulse Width Deassert Pulse Width HI t DACK Deassert to Next DREQ ...
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... PULSE t DACKSU (EMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0 Rev Page DREQWAIT Typ Max 15 3.5 × JCLK + 7.5 ns 9.7 3.5 × JCLK + 7 DREQWAIT ADV202 Unit 2 JCLK cycles JCLK cycles JCLK cycles JCLK cycles JCLK cycles ...
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... ADV202 t DREQRTN DREQ DACK RD HDATA t RD Figure 17. Burst Read Cycle for DREQ / DACK DMA Mode for Assigned DMA Channel t DREQRTN DREQ DACK RDFB HDATA DACKSU EMOD0/EDMOD1 <14:11> Programmed to a Value of 0000) t DACKSU Figure 18. Burst Read Cycle, Fly-By DMA Mode ( DREQ Pulse Width Is Programmable) Rev ...
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... Figure 19. Streaming Mode Timing—Encode Mode JDATA Output HD HOLD HD HOLD SU Figure 20. Streaming Mode Timing—Decode Mode JDATA Input Rev Page Typ Max 2.5 × JCLK + 7.0 ns 2.5 × JCLK + .7.0 ns HOLD HD Min Typ Max ADV202 Unit 1 JCLK cycles JCLK cycles Unit ...
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... ADV202 Parameter Description FIELD FIELD Hold from Rising VCLK HD FIELD VCLK to FIELD Valid TD SYNC DELAY Decode Data Sync Delay for HD Input with EAV/SAV Codes Decode Data Sync Delay for SD Input with EAV/SAV Codes Decode Data Sync Delay for DUAL_LANE (Extended) Input ...
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... VSTRB Setup to Rising VCLK SU VSTRB VSTRB Hold from Rising VCLK HD VCLK VDATA PIXEL N–1 N DATA(IN) VFRM SU VFRM(IN) VRDY VSTRB VCLK PIXEL N N DATA VFRM(OUT) HD VDATA VFRM HD VSTRB HD VSTRB SU VDATA VRFM TD Figure 22. Raw Pixel Mode Timing Rev Page Min Typ Max VRDY TD 2 ADV202 Unit ...
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... ADV202 SPI PORT TIMING Table 13. Parameter Description SCLK S_CLK Fall Time FALL SCLK S_CLK Rise Time RIS SCLK_hi SCLK high time SCLK_lo SCLK Low Time Data_su Data Setup Time Data_hd Data Hold Time CSEL_ Active Setup Time SU CSEL_ Active Hold Time ...
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... H10 88 H11 Rev Page ADV202 Pin Description DGND DGND IOVDD VCLK FIELD DGND DGND HDATA[19]_VDATA[15] HDATA[20]_VDATA[16] HDATA[21]_VDATA[17] DGND DGND DGND DREQ0 DACK0 DREQ1 DGND DGND HDATA[22]_VDATA[18] HDATA[23]_VDATA[19] HDATA[24]_VDATA[20]_JDATA[0] DGND DGND DGND IOVDD DACK1 IRQ DGND HDATA[28]_JDATA[4] HDATA[27]_VDATA[23]_JDATA[3] HDATA[26]_VDATA[22]_JDATA[2] HDATA[25]_VDATA[21]_JDATA[1] IOVDD DGND ...
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... ADV202 Pin No. Pin Location Pin Description 98 J10 TEST3 99 J11 DGND 100 K1 SCOMM[4] 101 K2 SCOMM[3] 102 K3 SCOMM[0] 103 K4 SCOMM[1] 104 K5 IOVDD 105 K6 IOVDD 106 K7 IOVDD 107 K8 ADDR[2] 108 K9 TEST2 109 K10 TEST5 Table 15. Pin BGA Assignments for 144-Lead Package Pin No. Pin Location ...
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... M2 135 M3 136 M4 137 M5 138 M6 139 M7 140 M8 141 M9 142 M10 143 M11 144 M12 Rev Page ADV202 Pin Description SCOMM[0] HDATA[31]_JDATA[7] IOVDD DGND VDD VDD DGND IOVDD TEST3 TEST2 TEST1 SCOMM[4] SCOMM[3] SCOMM[2] IOVDD DGND VDD VDD DGND IOVDD TEST5 RESET ...
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... PLL_HI register, Bit 4, must be set to 1. G10 O Interrupt. This pin indicates that the ADV202 requires the attention of the host processor. This pin can be programmed to indicate the status of the internal interrupt conditions within the ADV202. The interrupt sources are enabled via bits in register EIRQIE. ...
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... When not used, this pin should be tied low. M4 I/O This pin must be used in multiple chip mode to align the outputs of two or more ADV202s. For details, see the Applications section and the ADV202 Multichip Application application note. When not used, this pin should be tied low LCODE Output in Encode Mode ...
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... ADV202 Pins 121-Pin Mnemonic Used Package VSYNC 1 D8 VFRM HSYNC 1 D9 VRDY FIELD 1 E10 VSTRB TEST1 1 J6 TEST2 1 K9 TEST3 1 J10 TEST4 1 L6 TEST5 1 K10 VDD A3, A8, D7, H7 DGND A1, A11, A4, A9, C1, C11, D6, E1, E5–E7, E11, F1, F5– F7, F11, G1, G5–G7, G11, ...
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... THEORY OF OPERATION The input video or pixel data is passed on to the ADV202’s pixel interface, where samples are de-interleaved and passed on to the wavelet engine, where each tile or frame is decomposed into subbands using the 5/3 or 9/7 filters. The resultant wavelet coefficients are then written to internal memory. The entropy codecs then code the image data so that it conforms to the JPEG2000 standard ...
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... See the ADV202 in HIPI Mode technical note for details on how to use the ADV202 in this mode. Host Bus Configuration For maximum flexibility, the host interface provides several configurations to meet particular system requirements ...
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... A 2-pin handshake is used to transfer data over this synchronous interface. VALID is used to indicate that the ADV202 is ready to provide or accept data and is always an output. HOLD is always an input and is asserted by the host if it cannot accept/provide data. For example, JDATA mode allows ...
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... ADV202 INTERNAL REGISTERS This section describes the internal registers of the ADV202. DIRECT REGISTERS The ADV202 has 16 direct registers, as listed in Table 18. The direct registers are accessed over the ADDR [3–0], HDATA[31…0 and ACK pins. Table 18. Direct Registers Address Name 0x00 PIXEL ...
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... Both 32-bit and 16-bit hosts can access the indirect registers. 32-bit hosts use the IADDR and IDATA registers, while the 16 bit hosts use IADDR, IDATA, and the stage register. For additional information on accessing and configuring these registers, see the ADV202 User’s Guide. Description Pixel/Video Format Horizontal Count ...
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... ADV202 PLL The ADV202 uses the PLL_HI and PLL_LO direct registers to configure the PLL. Any time the PLL_LO register is modified, the host must wait at least 20 µs before reading or writing any other register. If this delay is not implemented, erratic behavior might result. The PLL can be programmed to have any possible final multiplier value as long as • ...
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... No-Boot Host Mode. ADV202 does not boot, but all internal registers and memory are accessible through normal host I/O operations. For details, see the ADV202 User’s Guide and the Getting Started with the ADV202 application note. SoC boot mode. The embedded software framework (ESF) takes control and establishes communications with the host ...
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... Input rate limits for HDATA might be less for certain applications depending on input picture size and content, host interface settings, and DMA transfer settings. Values in brackets refer to the 135 MHz speed grade version of the ADV202. 2 Minimum peak output rate or guaranteed sustained output rate. ...
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... Table 24. Maximum Supported Tile Width for Data Input on HDATA and VDATA Buses Compression Mode Input Format 9/7i Single-component 9/7i Two-component 9/7i Three-component 5/3i Single-component 5/3i Two-component 5/3i Three-component 5/3r Single-component 5/3r Two-component 5/3r Three-component Tile/Precinct Maximum Width 2048 1024 each 1024 (Y) 4096 2048 (each) 2048 (Y) 4096 2048 1024 Rev Page ADV202 ...
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... ADV202 JPEG2000 video processor. ENCODE—MULTICHIP MODE Due to the data input rate limitation (see Table 23), an 1080i application requires at least two ADV202s to encode or decode full-resolution 1080i video. In encode mode, the ADV202 accepts Y and CbCr data on separate buses. The input data must be in EAV/SAV format ...
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... D[9:0] SDATA SCK slave/slave configuration, the common HVF for both ADV202s is generated by an external house sync and each SCOMM[5] is connected to the same GPIO output on the host. SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be unmasked on both devices to enable multichip mode. ADV202 74 ...
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... ADV202 ENCODE/DECODE SDTV VIDEO APPLICATION Figure 28 shows two ADV202 chips using 10-bit CCIR656 in normal host mode. ENCODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] DECODE MODE 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ADV202 VDATA[11:2] VCLK MCLK HDATA[31:0] INTR IRQ ADDR[3: ACK ACK ADV202 ...
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... ASIC APPLICATION (32-BIT HOST/32-BIT ASIC) Figure 29 shows two ADV202 chips using 10-bit CCIR656 in normal host mode. ASIC DREQ0 DACK0 DATA[31:0] 32-BIT HOST CPU DATA[31:0] ADDR[3:0] ASIC DREQ0 DACK0 DATA[31:0] 31 -BIT HOST CPU DATA[31:0] ADDR[3:0] ADV202 DREQ0 DACK0 VDATA[11:2] VCLK HDATA[31:0] MCLK ...
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... MCLK Figure 30. Host Interface—Pixel Interface mode ADV202 YCrCb JDATA[7:0] VDATA[11:2] HOLD FIELD VALID VSYNC HSYNC VCLK MCLK HDATA[15:0] IRQ IRQ ADDR[3: ACK ACK Figure 31. JDATA Application Rev Page ADV202 RAW PIXEL DATAPATH COMPRESSED DATAPATH ADV7189 P[19:10] VIDEO IN FIELD VS HS LLC1 ...
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... Figure 33. 144-Lead Chip Scale Package Ball Grid Array [CSPBGA] (BC-144-3) Dimensions shown in millimeters Rev Page CORNER INDEX AREA BOTTOM VIEW * 1.31 DETAILA 1.21 1.11 0.20 NOM SEATING COPLANARITY PLANE A1 CORNER INDEX AREA BOTTOM VIEW * 1.32 1.21 1.11 COPLANARITY 0.20 MAX SEATING PLANE ADV202 ...
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... ADV202BBCZ-135 –40°C to +85°C ADV202BBC-150 –40°C to +85°C ADV202BBCZ-150 1 –40°C to +85°C ADV202-HD-EB ADV202-SD- Pb-free part. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Speed Grade Operating Voltage 115 MHz 1 ...