ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 34

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
APPLICATIONS
This section describes typical video applications for the
ADV202 JPEG2000 video processor.
ENCODE—MULTICHIP MODE
Due to the data input rate limitation (see Table 23), an 1080i
application requires at least two ADV202s to encode or decode
full-resolution 1080i video. In encode mode, the ADV202
accepts Y and CbCr data on separate buses. The input data must
be in EAV/SAV format. An encode example is shown in
Figure 25.
32-BIT HOST CPU
DATA[31:0]
ADDR[3:0]
DREQ
DACK
DREQ
DACK
G I/O
ACK
ACK
IRQ
IRQ
WR
WR
RD
RD
CS
CS
Figure 25. Encode—Multichip Application
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
_1_SLAVE
_2_SLAVE
ADV202
ADV202
Rev. B | Page 34 of 40
VDATA[11:2]
VDATA[11:2]
HSYNC
HSYNC
VSYNC
VSYNC
MCLK
FIELD
MCLK
FIELD
VCLK
VCLK
In decode mode, a master/slave configuration (as shown in
Figure 26) or a slave/slave configuration can be used to
synchronize the outputs of the two ADV202s. See the ADV202
Multichip Application application note for details on how to
configure the ADV202s in a multichip application.
Applications that have two separate VDATA outputs sent to an
FPGA or buffer before they are sent to an encoder do not
require synchronization at the ADV202 outputs.
CbCr
Y
CbCr
LLC
Y[9:0]
C[9:0]
10-BIT SD/HD
ADV7402
DECODER
VIDEO
1080i
VIDEO OUT