ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 15

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

STREAMING MODE (JDATA)—FIFO READ/WRITE
Table 10.
Parameter
JDATA
VALID
HOLD
HOLD
JDATA
JDATA
1
VDATA MODE TIMING
Table 11.
Parameter
VDATA
VDATA
VDATA
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
FIELD
For a definition of JCLK, see the
SU
SU
HD
TD
TD
SU
HD
SU
HD
TD
TD
SU
HD
SU
HD
TD
JDATA
JDATA
MCLK
VALID
MCLK
VALID
HOLD
HOLD
Description
MCLK to JDATA Valid
MCLK to VALID Assert/ Deassert
HOLD Setup to Rising MCLK
HOLD Hold from Rising MCLK
JDATA Setup to Rising MCLK
JDATA Hold from Rising MCLK
Description
VCLK to VDATA Valid Delay (VDATA Output)
VDATA Setup to Rising VCLK (VDATA Input)
VDATA Hold from Rising VCLK (VDATA Input)
HSYNC Setup to Rising VCLK
HSYNC Hold from Rising VCLK
VCLK to HSYNC Valid Delay
VSYNC Setup to Rising VCLK
VSYNC Hold from Rising VCLK
VCLK to VSYNC Valid Delay
FIELD Setup to Rising VCLK
JDATA
VALID
PLL
TD
SU
section.
JDATA
VALID
JDATA
TD
TD
HD
Figure 19. Streaming Mode Timing—Encode Mode JDATA Output
Figure 20. Streaming Mode Timing—Decode Mode JDATA Input
JDATA
JDATA
HD
SU
HOLD
HOLD
Rev. B | Page 15 of 40
SU
SU
HOLD
HD
Min
1.5
1.5
3
3
3
3
HOLD
HD
Typ
Min
4
4
3
4
3
4
4
2.5 × JCLK + 7.0 ns
2.5 × JCLK + .7.0 ns
Max
Typ
Max
12
12
12
Unit
JCLK cycles
JCLK cycles
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADV202
1