ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 30

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
PLL
The ADV202 uses the PLL_HI and PLL_LO direct registers to
configure the PLL. Any time the PLL_LO register is modified,
the host must wait at least 20 µs before reading or writing any
other register. If this delay is not implemented, erratic behavior
might result.
The PLL can be programmed to have any possible final
multiplier value as long as
• JCLK > 50 MHz and < 150 MHz (144-pin version).
• JCLK > 50 MHz and < 135 MHz (144-pin version).
• JCLK > 50 MHz and < 115 MHz (121-pin version).
• HCLK < 115 MHz.
• JCLK ≥ 2 × VCLK for single-component input.
• JCLK ≥ 2 × VCLK for YCrCb [4:2:2] input.
• In JDATA mode (JDATA), JCLK must be 4 × MCLK or
Table 20. Recommended PLL Register Settings
IPD
0
0
0
0
1
1
1
1
Table 21. Recommended Values for PLL_HI and PLL_LO Registers
Video Standard
SMPTE125M or ITU-R.BT656 (NTSC or PAL)
SMPTE293M (525p)
ITU-R.BT1358 (625p)
SMPTE274M (1080i)
higher.
LFB
0
0
1
1
0
0
1
1
PLLMULT
N
N
N
N
N
N
N
N
CLKIN Frequency on MCLK
27 MHz
27 MHz
27 MHz
74.25 MHz
Rev. B | Page 30 of 40
HCLKD
0
1
0
1
0
1
0
1
• The maximum burst frequency for external DMA modes is
• For MCLK frequencies greater than 50 MHz, the input clock
• IPD cannot be enabled for MCLK frequencies below 20 MHz.
To achieve the lowest power consumption, an MCLK frequency
of 27 MHz is recommended for a standard definition CCIR656
input. The PLL circuit is recommended to have a multiplier of 3.
This sets JCLK and HCLK to 81 MHz.
MCLK
divider must be enabled, that is, IPD set to 1.
≤ 0.36 JCLK.
Figure 24. PLL Architecture and Control Functions
IPD
÷
2
DETECT
PHASE
HCLK
N × MCLK
N × MCLK/2
2 × N × MCLK
N × MCLK
N × MCLK/2
N × MCLK/4
N × MCLK
N × MCLK/2
PLL_HI
0x0008
0x0008
0x0008
0x0008
LFB
÷
2
BYPASS
LPF
÷
PLLMULT
VCO
JCLK
N × MCLK
N × MCLK
2 × N × MCLK
2 × N × MCLK
N × MCLK/2
N × MCLK/2
N × MCLK
N × MCLK
PLL_LO
0x0004
0x0004
0x0004
0x0084
HCLKD
÷2
JCLK
HCLK