ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 22

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
PIN FUNCTION DESCRIPTIONS
Table 16.
Mnemonic
MCLK
RESET
HDATA<15:0>
ADDR<3:0>
CS
WE
RDFB
RD
WEFB
ACK
IRQ
DREQ0
FSRQ0
VALID
CFG<1>
DACK0
Pins
Used
1
1
16
4
1
1
1
1
1
1
1
121-Pin
Package
L9
L7
D4–D1, C5–
C3, B5, B4, C2,
B3–B1, A2,
A6–A5
H11, K8, H10,
J9
J8
J7
H9
H8
G10
F8
F9
144-Pin
Package
L12
L11
F4, E1–E3,
D1–D3, C1–
C3, B1–B3, A2,
A3, A4
J12, J11, J10,
H12
H11
H10
G12
G11
G10
F12
F11
Rev. B | Page 22 of 40
I/O
I
I
I/O
I
I
I
I
O
O
O
O
O
I
I
System Input Clock. For details, see the PLL section. Maximum input
frequency on MCLK is 74.25 MHz.
Reset. Causes the ADV202 to immediately reset. CS, RD, WE, DACK0,
DACK1, DREQ0, and DREQ1 must be held high when a RESET is
applied.
Host Data Bus. With HDATA<23:16>, <27:24>, <31:28>, these pins
make up the 32-bit wide host data bus. The async host interface is
interfaced together with ADDR<3:0>, CS, WE, RD, and ACK.
Unused HDATA pins should be pulled down via a 10 kΩ resistor.
Address Bus for the Host Interface.
Chip Select.This signal is used to qualify addressed read and write
access to the ADV202 using the host interface.
Write Enable Used with the Host Interface.
Read Enable when Fly-By DMA Is Enabled.
Note: Simultaneous assertion of WE and DACK low activates the
HDATA bus, even if the DMA channels are disabled.
Read Enable Used with the Host Interface.
Write Enable when Fly-By DMA Is Enabled.
Note: Simultaneous assertion of RD and DACK low activates the
HDATA bus, even if the DMA channels are disabled.
Acknowledge. Used for direct register accesses. This signal indicates
that the last register access was successful.
Note: Due to synchronization issues, control and status register
accesses might incur an additional delay, so the host software should
wait for acknowledgment from the ADV202.
Accesses to the FIFOs (external DMA modes), on the other hand, are
guaranteed to occur immediately, provided that space is available,
and should not wait for ACK, provided that the timing constraints
are observed.
If ACK is shared with more than one device, ACK should be connected
to a pull-up resistor (10 kΩ) and the PLL_HI register, Bit 4, must be set
to 1.
Interrupt. This pin indicates that the ADV202 requires the attention of
the host processor. This pin can be programmed to indicate the status
of the internal interrupt conditions within the ADV202. The interrupt
sources are enabled via bits in register EIRQIE.
Data Request for external DMA Interface. Indicates that the ADV202
is ready to send/receive data to/from the FIFO assigned to DMA
Channel 0.
Used in DCS-DMA Mode. Service request from the FIFO assigned to
Channel 0 (asynchronous mode).
Valid Indication for JDATA Input/Output Stream. Polarity of this pin is
programmable in the EDMOD0 register. VALID is always an output.
Boot Mode Configuration. This pin is read on reset to determine the
boot configuration of the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface. Signal from the host
CPU, which indicates that the data transfer request (DREQ0) has been
acknowledged and data transfer can proceed. This pin must be held
high at all times, if the DMA interface is not used, even if the DMA
channels are disabled.
Description