ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 8

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
DREQ / DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter
DREQ
t
t
t
t
DACK
DACK
t
WFSRQ
t
1
2
DREQ
WE SU
SU
HD
WE HD
DREQ RTN
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the PLL section.
PULSE
LO
HI
1
HDATA
HDATA
DREQ
DACK
DREQ
DACK
WE
WE
Description
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
WE to DACK Setup
Data to DACK Deassert Setup
Data to DACK Deassert Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
WE Hold after DACK Deassert
WE Assert to FSRQ Deassert (FIFO Full)
DACK to DREQ Deassert (DR × PULS = 0)
DREQ
t
t
WESU
WESU
Figure 5. Single Write for DREQ / DACK DMA Mode for Assigned DMA Channel
Figure 6. Single Write for DREQ / DACK DMA Mode for Assigned DMA Channel
PULSE
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
DACK
DACK
t
t
SU
SU
t
t
LO
LO
DREQ
DREQRTN
0
0
t
t
DACK
HD
DACK
HD
HI
HI
Rev. B | Page 8 of 40
1
1
Min
1
2.5
0
2
2
2
2
0
1.5
2.5
2
Typ
2
t
t
WEHD
WEHD
Max
15
3.5 × JCLK + 7.5 ns
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
3
Unit
JCLK cycles
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
ns
JCLK cycles
JCLK cycles
2