ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 10

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
DREQ/DACK DMA MODE—SINGLE FIFO READ OPERATION
Table 7.
Parameter
DREQ
t
t
t
t
DACK
DACK
t
RDFSRQ
t
1
2
DREQ
RD SU
RD
HD
RD HD
DREQ RTN
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
For a definition of JCLK, see the
PULSE
LO
HI
HDATA
HDATA
DREQ
DACK
DREQ
DACK
RD
RD
Description
DREQ Pulse Width
DACK Assert to Subsequent DREQ Delay
RD to DACK Setup
DACK to Data Valid
Data Hold
DACK Assert Pulse Width
DACK Deassert Pulse Width
RD Hold after DACK Deassert
RD Assert to FSRQ Deassert (FIFO Empty)
DACK to DREQ Deassert (DR × PULS = 0)
PLL
section.
DREQ
t
t
Figure 10. Single Read for DREQ / DACK DMA Mode for Assigned DMA Channel
Figure 9. Single Read for DREQ / DACK DMA Mode for Assigned DMA Channel
RDSU
RDSU
1
PULSE
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
DACK
DACK
t
t
RD
RD
t
LO
t
LO
DREQ
DREQRTN
0
0
DACK
DACK
t
t
HD
HD
HI
HI
Rev. B | Page 10 of 40
1
1
Min
1
2.5
0
2.5
1.5
2
2
0
1.5
2.5
2
2
Typ
t
t
RDHD
RDHD
Max
15
3.5 × JCLK + 7.5 ns
11
2.5 × JCLK + 7.5 ns
3.5 × JCLK + 7.5 ns
Unit
JCLK cycles
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
ns
JCLK cycles
JCLK cycles
2