ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 13

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter
DREQ
t
t
t
t
RD
RD
t
1
2
3
DREQ RTN
DACK
RD
HD
DREQ WAIT
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the
If sufficient data is available in FIFO.
LO
HI
SU
PULSE
HDATA
HDATA
Description
DREQ Pulse Width
DACK to DREQ Deassert (DR × PULS = 0)
DACK to RD Setup
DACK to Data Valid
Data Hold
RD Assert Pulse Width
RD Deassert Pulse Width
DACK Deassert to Next DREQ
WEFB
DREQ
DACK
DREQ
DACK
RD
PLL
section.
1
Figure 16. Burst Read Cycle for DREQ / DACK DMA Mode for Assigned DMA Channel
DREQ
t
RD
t
DREQRTN
PULSE
t
t
t
SU
DACKSU
DACKSU
0
0
(EMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0
t
t
HD
HD
Figure 15. Burst Write Cycle for Fly-By DMA Mode
( DREQ Pulse Width Is Programmable)
1
1
Rev. B | Page 13 of 40
WE
RD
LO
LO
13
13
1
2.5
0
2.5
2.5
1.5
1.5
2.5
Min
14
14
WE
RD
HI
HI
Typ
15
15
15
3.5 × JCLK + 7.5 ns
9.7
3.5 × JCLK + 7.5 ns
Max
t
t
DREQWAIT
DREQWAIT
3
JCLK cycles
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
Unit
ADV202
2