ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 12

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
EXTERNAL DMA MODE—FIFO WRITE, BURST MODE
Table 8.
Parameter
DREQ
t
t
t
t
WE
WE
t
1
2
3
DREQ RTN
DACK SU
SU
HD
DREQ WAIT
Applies to assigned DMA channel, if EDMOD0 or EDMOD1 <14:11> is programmed to a value that is not 0. Pulse width depends on the value programmed.
For a definition of JCLK, see the
If sufficient space is available in FIFO.
LO
HI
PULSE
HDATA
HDATA
DREQ
DACK
DREQ
DACK
Desription
DREQ Pulse Width
DACK to DREQ Deassert (DR × Pulse = 0)
DACK to WE Setup
Data Setup
Data Hold
WE Assert Pulse Width
WE Deassert Pulse Width
DACK Deassert to Next DREQ
WE
WE
PLL
section.
1
DREQ
Figure 14. Burst Write Cycle for DREQ /DMA Mode for Assigned DMA Channel
Figure 13. Burst Write Cycle for DREQ /DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1 <14:11> NOT Programmed to a Value of 0000)
t
t
PULSE
t
t
SU
SU
t
DACKSU
DACKSU
DREQRTN
(EDMOD0/EDMOD1 <14:11> Programmed to a Value of 0000)
0
0
t
t
HD
HD
1
1
Rev. B | Page 12 of 40
WE
WE
LO
LO
13
13
Min
1
2.5
0
2.5
2
1.5
1.5
2.5
14
14
WE
WE
HI
HI
Typ
15
15
Max
15
3.5 × JCLK + 7.5 ns
4.5 × JCLK + 7.5 ns
t
t
DREQWAIT
DREQWAIT
3
Unit
JCLK cycles
JCLK cycles
ns
ns
ns
JCLK cycles
JCLK cycles
JCLK cycles
2