ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 35

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM[5] pin is connected to the same GPIO on the
host.
DIGITAL STILL CAMERA/CAMCORDER
Figure 27 is a typical configuration for a digital camera or camcorder.
AD9843A
32-BIT HOST CPU
DATA[31:0]
SDATA
ADDR[3:0]
D[9:0]
SCK
SL
DREQ
DACK
DREQ
DACK
G I/O
ACK
ACK
IRQ
IRQ
WR
WR
CS
RD
CS
RD
10
Figure 26. Decode —Multichip Master/Slave Application
DATA INPUTS[9:0]
SERIAL DATA
SERIAL CLK
SERIAL EN
Figure 27. Digital Still Camera/Camcorder Application
FPGA
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
DREQ
DACK
SCOMM[5]
SCOMM[5]
_1_MASTER
_2_SLAVE
ADV202
ADV202
Rev. B | Page 35 of 40
VDATA[11:2]
VDATA[11:2]
VSYNC
HSYNC
HSYNC
VSYNC
MCLK
FIELD
MCLK
FIELD
VCLK
VCLK
MCLK
VCLK
VFRM
VRDY
VSTRB
VDATA[11:2]
Y
In a slave/slave configuration, the common HVF for both
ADV202s is generated by an external house sync and each
SCOMM[5] is connected to the same GPIO output on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
CbCr
ADV202
74.25MHz
HDATA[15:0]
OSC
ADDR[3:0]
CbCr
ACK
IRQ
Y
WE
RD
CS
CLKIN
Y[9:0]
C[9:0]
10-BIT SD/HD
ADV730xA
DECODER
VIDEO
DATA[15:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
HOST CPU
16-BIT
1080i
VIDEO OUT
ADV202