ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 23

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

Mnemonic
HOLD
FCS0
DREQ1
FSRQ1
CFG<2>
DACK1
FCS1
HDATA<31:28>
JDATA<7:4>
HDATA<27:24>
JDATA<3:0>
VDATA<23:20>
HDATA<23:16>
VDATA<19:12>
SCOMM<7>
SCOMM<6>
SCOMM<5>
SCOMM<4>
SCOMM<3>
SCOMM<2>
SCOMM<1>
SCOMM<0>
VCLK
VDATA<11:0>
Pins
Used
1
1
4
4
8
8
1
12
121-Pin
Package
F10
G9
J2–J4, H1
H2–H4, G4
G3, G2, F4, F3,
F2 E2, E3, E4
L2
L3
L4
K1
K2
L5
K4
K3
E9
D11, D10, C7,
C9, C10, B7,
B8, B9, B11,
B10, A7, A10
144-Pin
Package
F10
F9
K3, J1–J3
J4, H1–H3
H4, G1–G4,
F1–F3
M2
M3
M4
L1
L2
L3
K1
K2
E12
D10–D12,
C10–C12,
B10–B12,
A9–A11
Rev. B | Page 23 of 40
I/O
I
I
O
O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
O
I
I/O
External Hold Indication for JDATA Input/Output Stream. Polarity is
programmable in the EDMOD0 register. This pin is always an input.
Used in DCS-DMA Mode. Chip select for the FIFO assigned to
Channel 0 (asynchronous mode).
Data Request for External DMA Interface. Indicates that the ADV202
is ready to send/receive data to/from the FIFO assigned to DMA
Channel 1.
Used in DCS-DMA Mode. Service request from the FIFO assigned to
Channel 1 (asynchronous mode).
Boot Mode Configuration. This pin is read on reset to determine the
boot configuration of the on-board processor. The pin should be tied
to IOVDD or DGND through a 10 kΩ resistor.
Data Acknowledge for External DMA Interface. Signal from the host
CPU, which indicates that the data transfer request (DREQ1) has been
acknowledged and data transfer can proceed. This pin must be held
high at all times unless a DMA or JDATA access is occurring. This pin
must be held high at all times, if the DMA interface is not used, even if
the DMA channels are disabled.
Used in DCS-DMA Mode. Chip select for the FIFO assigned to
Channel 1 (asynchronous mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Host Expansion Bus.
JDATA Bus (JDATA Mode).
Video Data Expansion Bus.
Host Expansion Bus.
Video Data Expansion Bus. Extended pixel interface mode. Used for
video formats that use Y and CrCb on separate buses.
When not used, this pin should be tied low.
When not used, this pin should be tied low.
This pin must be used in multiple chip mode to align the outputs of
two or more ADV202s. For details, see the Applications section and
the ADV202 Multichip Application application note. When not used,
this pin should be tied low.
LCODE Output in Encode Mode. When LCODE is enabled, the output
on this pin indicates on a high transition that the last data-word for a
field has been read from the FIFO. For an 8-bit interface, such as
JDATA, LCODE is asserted for four consecutive bytes and is enabled
by default.
SPI interface: S_CSEL. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_MO. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_MI. When not used, this pin should be tied low.
Used only with boot mode 6.
SPI interface: S_CLK. When not used, this pin should be tied low.
Used only with boot mode 6.
Video Data Clock. Must be supplied, if video data is input/output on
the VDATA bus.
Video Data. Unused pins should be pulled down via a 10 kΩ resistor.
Description
ADV202