ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 2

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
TABLE OF CONTENTS
General Description ......................................................................... 3
Specificatons...................................................................................... 4
Pin BGA Assignments and Function Descriptions.................... 19
Theory of Operation ...................................................................... 25
ADV202 Interface........................................................................... 26
REVISION HISTORY
1/05—Rev. A to Rev. B
Updated Outline Dimensions ....................................................... 39
JPEG2000 Feature Support.......................................................... 3
Supply Voltages and Current....................................................... 4
Input/Output Specifications........................................................ 4
Clock and RESET Specifications ................................................ 5
Normal Host Mode—Read Operation ...................................... 6
Normal Host Mode—Write Operation ..................................... 7
DREQ / DACK DMA Mode—Single FIFO Write Operation .. 8
DREQ / DACK DMA Mode—Single FIFO Read Operation . 10
External DMA Mode—FIFO Write, Burst Mode................... 12
External DMA Mode—FIFO Read, Burst Mode.................... 13
Streaming Mode (JDATA)—FIFO Read/Write ...................... 15
VDATA Mode Timing ............................................................... 15
Raw Pixel Mode Timing ............................................................ 17
SPI Port Timing .......................................................................... 18
Pin BGA Assignments ............................................................... 19
Pin Function Descriptions ........................................................ 22
Wavelet Engine ........................................................................... 25
Entropy Codecs........................................................................... 25
Embedded Processor System .................................................... 25
Memory System .......................................................................... 25
Internal DMA Engine ................................................................ 25
Rev. B | Page 2 of 40
Internal Registers............................................................................ 28
Video Input Formats ...................................................................... 32
Applications..................................................................................... 34
Outline Dimensions ....................................................................... 39
12/04—Rev. 0 to Rev. A
Changes to Features ..........................................................................1
Changes to Table 2.............................................................................4
Changes to Table 16 ....................................................................... 24
Changes to Table 23 ....................................................................... 32
7/04—Revision 0: Initial Version
Video Interface (VDATA Bus).................................................. 26
Host Interface (HDATA Bus) ................................................... 26
Direct and Indirect Registers .................................................... 26
Control Access Registers ........................................................... 27
Pin Configuration and Bus Sizes/Modes ................................ 27
Stage Register .............................................................................. 27
JDATA Mode............................................................................... 27
External DMA Engine ............................................................... 27
SPI Port ........................................................................................ 27
Direct Registers........................................................................... 28
Indirect Registers........................................................................ 29
PLL ............................................................................................... 30
Hardware Boot............................................................................ 31
Encode—Multichip Mode......................................................... 34
Decode—Multichip Master/Slave ............................................ 35
Digital Still Camera/Camcorder .............................................. 35
Encode/Decode SDTV Video Application.............................. 36
ASIC Application (32-Bit Host/32-Bit ASIC) ......................... 37
HIPI (Host Interface—Pixel Interface) ................................... 38
JDATA Interface ......................................................................... 38
Ordering Guide .......................................................................... 40