ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 28

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ADV202-SD-EB

Manufacturer Part Number
ADV202-SD-EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV202-SD-EB

Lead Free Status / Rohs Status
Not Compliant
ADV202
INTERNAL REGISTERS
This section describes the internal registers of the ADV202.
DIRECT REGISTERS
The ADV202 has 16 direct registers, as listed in Table 18. The
direct registers are accessed over the ADDR [3–0],
HDATA[31…0], CS , RD , WR , and ACK pins.
Table 18. Direct Registers
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Name
PIXEL
CODE
ATTR
ANCL
CMDSTA
EIRQIE
EIRQFLG
SWFLAG
BUSMODE
MMODE
STAGE
IADDR
IDATA
BOOT
PLL_HI
PLL_LO
Description
Pixel FIFO Access Register
Compressed Code Stream Access Register
Attribute FIFO Access Register
Ancillary FIFO Access Register
Command Stack
External Interrupt Enabled
External Interrupt Flags
Software Flag Register
Bus Mode Configuration Register
Miscellaneous Mode Register
Staging Register
Indirect Address Register
Indirect Data Register
Boot Mode Register
PLL Control Register—High Byte
PLL Control Register—Low Byte
Rev. B | Page 28 of 40
The host must first initialize the direct registers before any
application-specific operation can be implemented.
For additional information on accessing and configuring these
registers, see the ADV202 User’s Guide.