ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 16

no-image

ADV202-SD-EB

Manufacturer Part Number
ADV202-SD-EB
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADV202-SD-EB

Lead Free Status / Rohs Status
Not Compliant
ADV202
Parameter
FIELD
FIELD
SYNC DELAY
HD
TD
VDATA(OUT)
VDATA(OUT)
VDATA(OUT)
VDATA(IN)
VDATA(IN)
HSYNC
HSYNC
VSYNC
VSYNC
VCLK
VCLK
VCLK
VCLK
VCLK
ENCODE CCIR-656 LINE
DECODE MASTER CCIR-656 LINE
DECODE SLAVE CCIR-656 LINE
DECODE SLAVE HVF MODE
ENCODE HVF MODE
*HSYNC AND VSYNC DO NOT HAVE TO BE APPLIED SIMULTANEOUSLY
Cr
Description
FIELD Hold from Rising VCLK
VCLK to FIELD Valid
Decode Data Sync Delay for HD Input with EAV/SAV Codes
Decode Data Sync Delay for SD Input with EAV/SAV Codes
Decode Data Sync Delay for DUAL_LANE (Extended) Input
Decode Data Sync Delay for HVF Input (from First Rising VCLK after
HSYNC Low to First Data Sample)
Y
Y
Cb
Cr
Y
Cr
Cr
VDATA
Y
VDATA
VDATA
Y
Y
Y
Cb
Cr
VDATA
VDATA
TD
TD
Cb
Cb
SU
Cb
Y
TD
HD
Y
Y
Cb
Y
Y
FF
Cr
Y
FF
FF
Y
Cb
Figure 21. Video Mode Timing
Rev. B | Page 16 of 40
EAV
Y
EAV
EAV
VSYNC
HSYNC
VSYNC
HSYNC
SYNC DELAY
SYNC DELAY
HD
SU
SU
HD
FF
*
*
FF
Min
3
Cb
SAV
FF
Cb
HSYNC
VSYNC
Y
Cb
SAV
Typ
7
9
7
10
HD
Y
HD
Cr
Y
Cb
Cr
SAV
Y
Cr
Max
12
Y
Y
Cb
Cb
Cr
Cb
Y
Unit
ns
VCLK cycles
VCLK cycles
VCLK cycles
VCLK cycles