ADV202-SD-EB Analog Devices Inc, ADV202-SD-EB Datasheet - Page 6

• Manufacturer Part Number: ADV202-SD-EB
• Manufacturer: Analog Devices Inc

Specifications of ADV202-SD-EB

• Lead Free Status / Rohs Status: Not Compliant

ADV202
NORMAL HOST MODE—READ OPERATION
Table 4.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
1
ACK
ACK
DRD
DRD
HZRD
SC
SA
HC
HA
RH
RL
RCYC
For a definition of JCLK, see the
[dir]
[dir]
[indir]
[indir]
HDATA
ADDR
ACK
Read Access Time, Indirect Registers
Description
RD to ACK, Direct Registers and FIFO Accesses
RD to ACK, Indirect Registers
Read Access Time, Direct Registers
Data Hold
CS to RD Setup
Address Setup
CS Hold
Address Hold
Read Inactive Pulse Width
Read Active Pulse Width
Read Cycle Time, Direct Registers
CS
RD
PLL
section.
t
t
SA
SC
t
t
ACK
DRD
t
RL
Figure 3. Normal Host Mode—Read Operation
VALID
t
Rev. B | Page 6 of 40
HC
t
t
HA
t
HZRD
RCYC
t
RH
Min
5 ns
10.5 × JCLK
5 ns
10.5 × JCLK
2
0
2
0
2
2.5
2.5
5.0
Typ
15.5 × JCLK + 7.0 ns
1.5 × JCLK + 7.0 ns
15.5 × JCLK + 7.0 ns
Max
1.5 × JCLK + 7.0 ns
8.5
Unit
ns
ns
ns
ns
ns
JCLK
JCLK
JCLK
1