AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet
AD9925BBCZ
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AD9925BBCZ Summary of contents
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FEATURES Integrated 10-channel V-driver Register-compatible with the AD9991 and AD9995 3-field (6-phase) vertical clock support 2 additional vertical outputs for advanced CCDs Complete on-chip timing generator Precision Timing core with <600 ps resolution Correlated double sampler (CDS ...
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AD9925 TABLE OF CONTENTS Specifications..................................................................................... 3 Digital Specifications........................................................................ 4 Vertical Driver Specifications ......................................................... 5 Analog Specifications....................................................................... 6 Timing Specifications....................................................................... 7 Absolute Maximum Ratings............................................................ 8 Package Thermal Characteristics ............................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Terminology .................................................................................... ...
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SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGES AVDD (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD ( Drivers) DRVDD (Data Output Drivers) DVDD (Digital) V-DRIVER SUPPLY VOLTAGES VDVDD (V-Driver Input ...
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AD9925 DIGITAL SPECIFICATIONS RGVDD = HVDD = DVDD = DRVDD = 2 3 Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance ...
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VERTICAL DRIVER SPECIFICATIONS VDVDD = 3 −7 Table 3. Parameter 3-LEVEL OUTPUTS (V1, V2, V3A, V3B, V5A, V5B) (Simplified Load Conditions, 6000 pF to Ground) Delay Time, ...
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AD9925 ANALOG SPECIFICATIONS AVDD1 = 3 MHz, typical timing specifications, T CLI Table 4. Parameter CDS Allowable CCD Reset Transient Maximum Input Range before Saturation 0 dB CDS Gain (Default Setting) −2 dB CDS Gain −4 ...
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TIMING SPECIFICATIONS pF, AVDD = DVDD = DRVDD = 3 Table 5. Parameter MASTER CLOCK, CLI (Figure 17) CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising Edge to Internal Pixel Position ...
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AD9925 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter With Min Respect To VDVDD VDVSS VDVSS – 0.3 VL VDVSS VDVSS – 10 VH1, VH2 VDVSS VL – 0.3 VM1, VM2 VDVSS VL – 0.3 AVDD AVSS –0.3 TCVDD TCVSS –0.3 HVDD ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Tab le 7. Pin Function Des criptions Pin No. Mnemo nic E1, F2, F3 HVSS G2, G3 HVSS H1, H2, H3 HVDD J2, J3 HVDD K2, L2 ...
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AD9925 Pin No. Mnemonic F9 HD F10 DVSS F11 DVDD E9 V5B D9 V5A E10 DCLK D11 D0 C10 D1 C11 D2 B10 D3 B11 D4 A10 V3B B9 V3A ...
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TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates ...
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AD9925 EQUIVALENT CIRCUITS AVDD R AVSS Figure 4. CCDIN DVDD DATA THREE- STATE DVSS Figure 5. Digital Data Outputs DVDD 330Ω DVSS Figure 6. Digital Inputs AVSS DRVDD RG DOUT THREE-STATE DRVSS Rev Page 12 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 450 V = 3.3V DD 400 V = 3.0V DD 350 300 250 200 150 18 24 SAMPLE RATE (MHz) Figure 9. Power vs. Sample Rate 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 ...
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AD9925 SYSTEM OVERVIEW Figure 14 shows the typical system block diagram for the AD9925 used in master mode. The CCD output is processed the AD9925’s AFE circuitr y, which consists of a CDS, VGA, black level clamp, and ADC. The ...
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PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9925 generates high speed timing signals using the flexi- ble Precision Timing core. This core is the foundation that gen- erates the timing used for both the CCD and the AFE: the reset ...
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AD9925 CCD SIGNAL PROGRAMMABLE CLOCK POSITIONS RISING EDGE FALLING EDGE. 3. SHP SAMPLE LOCATION. 4. SHD SAMPLE LOCATION RISING EDGE POSITION AND 6: H1 FALLING ...
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CCD SIGNAL RG H1/H3 H2/H4 NOTE 1. USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING. Table 9. Precision Timing Edge Locations Quadrant Edge Location (Dec ...
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AD9925 P[0] PIXEL PERIOD DCLK t OD DOUT NOTES 1. DATA OUTPUT (DOUT) AND DCLK PHASE IS ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS. t ...
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These lines will not contain an activ e CLPOB ulse. CLP p MASKTYPE is set l mode of oper ion. at Second CLPMA SK re gisters can be used ...
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AD9925 Table 11. HBLK Pattern Registers Register Length Range HBLKMASK 1 b High/Low H3HBLKOFF 1 b High/Low HBLKALT Alternation Mode HBLKTOG1 4095 Pixel Location HBLKTOG2 4095 Pixel ...
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HBLK H1/H3 H2/H4 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS Increasing H-Clock Width during HBLK The AD9925 will also allow the pulse width to be increased during the HBLK interval. The H-clock pu can ...
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AD9925 28 DUMMY PIXELS OPTICAL BLACK HD CCDIN VERTICAL SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB VERTICAL TIMING GENERATION The AD9925 provides a very flexible solution for generating vertical CCD timing and can support multiple CCDs and dif- ferent ...
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CREATE THE VERTICAL PAT TERN GROUPS 1 (MAXIMUM OF 10 GROUPS) XV1 XV2 XV3 VPAT 0 XV4 XV5 XV6 XV1 XV2 XV3 VPAT 9 XV4 XV5 XV6 USE THE MODE REGISTER TO CONTROL WHICH FIELDS 3 ARE USED, AND IN ...
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AD9925 Vertical Pattern Groups (VPAT) The vertical pattern groups define the individual pulse patterns for each XV1 to XV6 output signal. Table 13 summarizes the registers available for generating each of the 10 vertical pattern groups. The start polarity (VPOL) ...
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Masking Using FREEZE/RESUME Registers As shown in Figure 33, the FREEZE/RESUME registers are us to temporarily mask the XV outputs. The pixel locations to begin the masking (FREEZE) and end the masking (RESUME) create an area in which the vertical ...
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AD9925 Hold Area Using FREEZE/RESUME Registers The FREEZE/RESUME registers can also be used to create a hold area, in which the XV outputs are temporarily held and then later continued starting at the point where they were held As shown ...
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Vertical Sequences (VSEQ) The vertical sequences are created by selecting one of the 10 ver- ti cal pattern groups and adding repeats, the start position, and horizontal clamping and blanking information verti- cal sequences may be programmed, ...
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AD9925 HD XV1 TO XV6 VERTICAL PATTERN GROUP CLPOB PBLK 6 HBLK PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE: 1. START POSITION IN THE LINE OF SELECTED VERTICAL PATTE 2. HD LINE LENGTH. 3. VERTICAL PATTERN SELECT (VPATSEL) TO SELEC 4. ...
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Complete Field: Combining Vertical Sequences After the vertical sequences have been created, they are combined to create different readout fields. A field consists seven different regions, and within each region, a different vertic sequence can be selected. ...
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AD9925 Generating Line Alternat ion for Vertical Sequence and HBLK During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9925 can support this by using the VPATREPO and VPATREPE registers This allows ...
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Sweep Mode Operation The AD9925 contains an additional mode of vertical timing operation called sweep mode. This mode is used to generate a large number of repetitive pulses that span across multiple HD lines. One example of where this mode ...
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AD9925 VD HD LINE 0 LINE 1 XV1 TO XV8 REGION 0 START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE VERTICAL SEQUENCE REGISTERS HD 3 VPATLEN PIXEL ...
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Table 17. SG Pattern Registers (Also See Field Registers in Table 15) Register Length Range SGPOL 1 b High/Low SGTOG1 4095 Pixel Location SGTOG2 4095 Pixel Location SGMASK_OVR 6 b Six Individual ...
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AD9925 EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2 MODE REGISTER CONTENTS = 0x60 0088 FIELD 0 EXAMPLE 2: TOTAL FIELDS = 2, FIRST FIELD = FIELD ...
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Figure 44. CCD Timing Example—Dividing Each Field into Regions Rev Page AD9925 N N– N–1 N– N–2 N– ...
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AD9925 SHUTTER TIMING C ONTROL The CCD image exposure time is controlled by the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9925 supports three types of electronic shuttering: normal, high precision, and ...
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VD HD XSG SUBCK NOTES 1. SECOND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE. 2. LOCATION OF SECOND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTER. TRIGGER EXPOSURE VD XSG SUBCK NOTES 1. SUBCK MAY BE ...
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AD9925 SUBCK Suppression Normally, the S UBC Ks wil l be gin to pulse on the line fol the sensor gate lin VSG some CCDs, the SUBCK pu e needs to be supp ress ed for ...
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TRIGGER VSUB VD XSG SUBCK 2 VSUB MODE 0 1 VSUB OPERATION: 1. ACTIVE POLARITY IS POLARITY (ABOVE EXAMPLE IS VSUB ACTIVE HIGH). 2. ON-POSITION IS PROGRAMMABLE, MODE 0 TURNS ON AT THE START OF EXPOSURE, MODE 1 TURNS ON ...
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AD9925 TRIGGER EXPOSURE AND STROBE VD XSG SUBCK STROBE 1 STROBE PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. ON-POSITION IS PROGRAMMABLE IN ANY FIELD DURING THE EXPOSURE TIME (WITH RESPECT TO THE FIELD CONTAINING THE LAST SUBCK). 3. OFF-POSITION IS PROGRAMMABLE ...
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EXAMPLE OF EXPO SURE AND READOUT OF INTE Figure 51. Example of Exposure and Still Image Readout Using Shutter Signals and MODE Register RLACED FRAME Rev Page AD9925 ...
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AD9925 Refer to Figure 51 for each step: 1. Write to the READOUT register (Addr x61) to specify the number of fields to further suppress SUBCK while the CCD data is readout. In this example, READOUT = 3. Write to ...
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FG_TRIG OPERATION The AD9925 contains an additional signal that may be used in conjunction with shutter operation or general system operation. The FG_TRIG signal is an internally generated pulse that can be output on the VSUB or SYNC pins for ...
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AD9925 VD MODE REGISTER FIELD 0 FIELD COUNT FG_TRIG 1 FG_TRIG PROGRAMMABLE SETTINGS: 1. ACTIVE POLARITY. 2. FIRST TOGGLE POSITION, LINE AND PIXEL LOCATION. 3. SECOND TOGGLE POSITION, LINE AND PIXEL LOCATION. 4. FIELD PLACEMENT BASED ON MODE REGISTER FIELD ...
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DC RESTORE 1.3V SHP SHD 0.1µF CCDIN CDS DOUT SHP SHD PHASE PRECISION CLI TIMING GENERATION ANALOG FRONT END DESCRIPTION AND OPERATION The AD9925 signal processing chain is shown in Figure 55. Each processing step is essential in achieving a ...
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AD9925 ADC The AD992 5 uses high perfo rmance ADC architecture, opti- mized fo r high sp eed and low power. Diff (D NL) performan ce is typically better than 0.5 LSB. The ADC uses put ...
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VERTICAL DRIVER SIGNAL CONFIGURATION As shown in Figure 57, XV1 to XV8, XSG1 to XSG6, and XSUBCK are outputs from the internal AD9925 timing genera- tor, while and SUBCK are the resulting outputs from the AD9925 vertical ...
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AD9925 Table 22. V1 Output Polarity V-Driver Input XV1 XSG1 Table 23. V2 Output Polarity V-Driver Input XV2 XSG6 Table 24. V3A Output Polarity ...
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XV1 XSG1 XV2 XSG6 XV3 XSG2 VH V3A VM VL XV3 XSG3 VH V3B VM VL Figure 58. XV1, XSG1, and V1 Output Polarities Figure 59. XV2, XSG6, and V2 Output Polarities ...
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AD9925 XV5 XSG4 VH V5A VM VL XV5 XSG5 VH V5B VM VL XV4, XV6, XV7, XV8 VM V4, V6, V7 Figure 62. XV5, XSG4, and V5 A Output Polarities Figure 63. XV5, X SG5, and V5B Output ...
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POWER-UP AND SYNCHRONIZATION Vertical Driver Power Supply Sequencing The recommended Power-Up and Power-Down sequences are shown in Figure 65 and Figure 66, respectively. As shown, the VM1 and VM2 voltage levels should never exceed the VH1 and VH2 voltage levels ...
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AD9925 0V POWER SUPPLIES 1 4 CLI (INPUT SERIAL WRITES SYNC (INPUT) VD (OUTPUT) HD (OUTPUT) DIGITAL OUTPUTS Figure 67. Recommended Power-Up Sequence and Synchronization, Master Mode Recommended Power-Up Sequence for Master Mode When the AD9925 is ...
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Table 33. Power-Up Register Write Sequence Address Data De scription 0x10 0x01 Re set All Registers to Default Va 0x0A to 0x0D TBD Standby V-Driver Input Signal Polarities 0x00 0x04 Power-Up the AFE and CLO Oscillator 0x7F 0x01 Select Register ...
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AD9925 SYNC VD HD H124, RG VSG, SUBCK NOTES 1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGIS 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESE 4. ...
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STANDBY MODE OPERATION The AD9925 contains three different standby modes to optimize the overall power dissipation in a particular application. Bits [1:0] of the OPRMODE register control the power-down state of the device: OPRMODE[1: Normal Operation (Full ...
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AD9925 Table 35. Standby Mode Operatio n—Vertical and Shutter Outputs (Pr I/O Block Standby 3 (Default) XV1 Low XV8 Low XV3 Low XV7 Low XV6 Low XSG6 Low XV5 Low XV4 Low XSG5 Low XSG4 Low XV2 Low XSG3 Low ...
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CIRCUIT LAYOUT INFORMATION The AD9925 typical circuit connections are shown in Figure 73. The PCB layout is critical in achieving good image quality from the AD9925. All of the supply pins, particularly the AVDD, TCVDD, RGVDD, and HVDD supplies, must ...
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AD9925 –7.5V SUPPLY +15V SUPPLY 0.1µF 0.1µF DCLK E10 DCLK TO ASIC/DSP D0 (LSB) D11 D1 C10 D2 C11 D3 B10 D4 B11 D5 A10 D10 B6 12 D11 (MSB) D ATA ...
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SERIAL INTERFACE TIMING All of the internal registers of the AD9925 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both t he 8-bit address and 24-bit data- word are written ...
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AD9925 Register Address BANK 1, BANK 2, and BANK 3 The AD99 5 address space is d vided into three 2 i ter b anks, r eferr Register Register B Regi ster Ba nk ...
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Updating New Register Values The AD99 5’s internal register are updated depe nding particular reg ister . Table 36 summ four differe nt ty pes of register u pda tes: 1. SCK U ...
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AD9925 COMPLETE LISTING FO R REGISTER BANK 1 All r egister s are V D updated, except where noted. L Table 37. AFE Register Map A ddress Data Bit Content Default Value 00 [11: [9: [7:0] ...
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Table 39. VD/HD Register Map Address Data Bit Content Default Value [11:0] 0 [17:12 [11:0] 0 Table 40. Timing Core Register Map Address Data Bit Content Default Value 30 [0] 0 ...
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AD9925 Table 42. SG Pattern Register Map Address Data Bit Content Default Value 50 [0] 1 [1] 1 [ [11:0] FFF [23:12] FFF 52 [11:0] FFF [23:12 [11:0] FFF [23:12] FFF 54 [11:0] ...
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Table 44. Register Map Selection Address Data Bit Content Default Value 7F [1:0] 0 Table 45. AFE Operation Register Detail Add ress Data Bi t Content De fault Value 00 [1:0] 3 [2] 1 [3] 0 [4] 0 [5] 0 ...
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AD9925 COMPLETE LISTING FOR REGISTER BAN All v ertical patter n group and v ertica l sequence re are undefin ed. Table 47. Vertical Pattern Group 0 (VPAT0) Regi Address Data Bit Content Default Value 00 [5:0] X [11:6] X ...
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Table 48. Vertical Pattern Group 1 (VPAT1) Register Map Address Data Bit Content Default Value 0C [5:0] X [11:6] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X ...
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AD9925 Table 49. Vertical Pattern Group 2 (VPAT2) Register Map Address Data Bit Content Default Value 18 [5:0] X [11:6] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] ...
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Table 50. Vertical Pattern Group 3 (VPAT3) Register Map Address Data Bit Content Default Value 24 [5:0] X [11:6] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X ...
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AD9925 Table 51. Vertical Pattern Group 4 (VPAT4) Register Map Address Data Bit Content Default Value 30 [5:0] X [11:6] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] ...
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Table 52. Vertical Pattern Group 5 (VPAT5) Register Map Address Data Bit Content Default Value 3C [5:0] X [11:6] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X ...
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AD9925 Table 53. Vertical Pattern Group 6 (VPAT6) Register Map Address Data Bit Content Default Value 48 [5:0] X [11:6] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] ...
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Table 54. Vertical Pattern Group 7 (VPAT7) Register Address Data Bit Content Default Value 54 [5:0] X [11 [23 1:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12 ...
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AD9925 Table 55. Vertical Pattern Group 8 (VPAT8) Register Add ress Data B it Content De fault Value 60 [5:0] X [11:6] X [23: [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12] ...
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Table 56. Vertical Pattern Group 9 (VPAT9) Register Address Data Bit Content D efault Value 70 [5:0] X [11 [23 1:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12] X ...
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AD9925 Table 58. Vertical Sequence 0 (VSEQ0) Register Map Address Data Bit Content Default Value 80 [1:0] X [2] X [3] X [7:4] X [9:8] X [11:10] X [12] X [23:12] 81 [11:0] X [23:12 [11:0] X [23:12] ...
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Table 60. Vertical Sequence 2 (VSEQ2) Register Map Address Data Bit Content Default Value 90 [1:0] X [2] X [3] X [7:4] X [9: 1:10] X [12] X [23: [11:0] X [23:12 [11:0] X ...
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AD9925 Table 62. Vertical Sequence 4 (VSEQ4) Register Map Address Data Bit Content Default Value A0 [1:0] X [2] X [3] X [7:4] X [9:8] X [11:10] X [12] X [23:12] A1 [11:0] X [23:12 [11:0] X [23:12] ...
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Table 64. Vertical Sequence 6 (VSEQ6) Register Map Address Data Bit Content Default Value B0 [1:0] X [2] X [3] X [7:4] X [9:8] X [11:10] X [12] X [23:12] B1 [11:0] X [23:12 [11:0] X [23:12] X ...
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AD9925 Table 66. Vertical Sequence 8 (VSEQ8) Register Map Address Data Bit Content Default Value C0 [1:0] X [2] X [3] X [7:4] X [9:8] X [11:10] X [12] X [23:12] C1 [11:0] X [23:12 [11:0] X [23:12] ...
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Table 68. Field 0 Register Map Address Data Bit Content Default Value D0 [3:0] X [4] X [5] X [9:6] X [10] X [11] X [15:12] X [16] X [17] X [21:18] X [22] X [23 [3:0] X ...
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AD9925 Table 69. Field 1 Register Map Address Data Bit Content Default Value D8 [3:0] X [4] X [5] X [9:6] X [10] X [11] X [15:12] X [16] X [17] X [21:18] X [22] X [23 [3:0] ...
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Table 70. Field 2 Register Map Address Data Bit Content Default Value E0 [3:0] X [4] X [5] X [9:6] X [10] X [11] X [15:12] X [16] X [17] X [21:18] X [22] X [23 [3:0] X ...
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AD9925 Table 71. Field 3 Register Map Address Data Bit Content Default Value E8 [3:0] X [4] X [5] X [9:6] X [10] X [11] X [15:12] X [16] X [17] X [21:18] X [22] X [23 [3:0] ...
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Table 72. Field 4 Register Map Address Data Bit Content Default Value F0 [3:0] X [4] X [5] X [9:6] X [10] X [11] X [15:12] X [16] X [17] X [21:18] X [22] X [23 [3:0] X ...
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AD9925 Table 73. Field 5 Register Map Address Data Bit Content Default Value F8 [3:0] X [4] X [5] X [9:6] X [10] X [11] X [15:12] X [16] X [17] X [21:18] X [22] X [23 [3:0] ...
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COMPLETE LISTING FOR REGISTER BANK 3 All vertical pattern group and vertical sequence registers are SCP updated. Default register values are undefined. Table 74. XV7 and XV8 Pattern Group 0 (VPAT0) Registers Address Data Bit Content Default Value 00 [0] ...
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AD9925 Table 76. XV7 and XV8 Pattern Group 2 (VPAT2) Registers Address Data Bit Content Default Value 10 [0] X [1] X [11:2] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12] ...
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Table 79. XV7 and XV8 Pattern Group 5 (VPAT5) Registers Address Data Bit Content Default Value 28 [0] X [1] X [11:2] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12] X ...
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AD9925 Table 82. XV7 and XV8 Pattern Group 8 (VPAT8) Registers Address Data Bit Content Default Value 40 [0] X [1] X [11:2] X [23:12 [11:0] X [23:12 [11:0] X [23:12 [11:0] X [23:12] ...
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Table 85. XV7 and XV8 Vertical Sequence 1 Registers Address Data Bit Content Default Value 54 [0] X [11:1] X [23:12 [11:0] X [23:12 [0] X [23: [23:0] X Table 86. XV7 and XV8 ...
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AD9925 Table 89. XV7 and XV8 Vertical Sequence 5 Registers Address Data Bit Content Default Value 64 [0] X [11:1] X [23:12 [11:0] X [23:12 [0] X [23: [23:0] X Table 90. XV7 and ...
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Table 93. XV7 and XV8 Vertical Sequence 9 Registers Address Data Bit Content Default Value 74 [0] X [11:1] X [23:12 [11:0] X [23:12 [0] X [23: [23:0] X Register Name Register Description HOLD_9 ...
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... AD9925 OUTLINE DIMENSIONS 1.40 MAX ORDERING GUIDE Models Temperature Range 1 AD9925BBCZ –25°C to +85° AD9925BBCZRL –25°C to +85° Pb-free part 8.00 BSC BALL A1 INDICATOR 6.50 BSC SQ TOP VIEW 0.65 BSC DETAIL A 0.40 0.25 0.45 0.40 0.35 BALL DIAMETER Figure 78. 96-Lead Chip Scale Package Ball Grid Array [CSP_BGA] ...
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NOTES Rev Page AD9925 ...
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AD9925 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04637–0–10/04(A) Rev Page ...