AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 25

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Masking Using FREEZE/RESUME Registers
As shown in Figure 33, the FREEZE/RESUME registers are us
to temporarily mask the XV outputs. The pixel locations to
begin the masking (FREEZE) and end the masking (RESUME)
create an area in which the vertical toggle positions are ignored
At the pixel location specified in the FREEZE register, the XV
outputs will be held static at their current dc state, high or low
The XV outputs are held until the pixel location specified by the
XV1
XV8
XV1
XV8
NOTES
1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING.
2. TWO SEPARATE MASKING AREAS ARE AVAILABLE FOR EACH VPAT GROUP, USING FREEZE1/RESUME1 AND FREEZE2/RESUME2 REGISTERS.
HD
HD
Figure 33. Vertical Masking Using the FREEZE/RESUME Registers
Figure 32. No Vertical Masking
FREEZE
Rev. A | Page 25 of 96
ed
.
.
NO MASKING AREA
FOR XV1 TO XV8
MASKING AREA
RESUME register is reached, at which point the signals will
c
FREEZE/RESUME registers are provided, allowing the vertical
o
a
g
re
Sequences (VSEQ) section.
ontinue with any remaining toggle positions. Two sets of
nd RESUME positions are programmed in the vertical pattern
utputs to be interrupted twice in the same line. The FREEZE
roup registers, but are enabled separately using the VMASK
gisters. The VMASK registers are described in the Vertical
RESUME
AD9925