AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 52

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9925
Recommended Power-Up Sequence for Master Mode
When the AD9925 is powered up, the following sequence is
recommended (refer to Figure 67 for each step). Note that a
SYNC signal is required for master mode operation. If an exter-
nal SYNC pulse is not available, it is also possible to generate an
internal SYNC pulse by writing to the SYNCPOL register, as
described in the next section.
1.
2.
3.
4.
5.
6.
Turn on power supplies for the AD9925 and apply master
clock CLI.
Reset the internal AD9925 registers by writing a 1 to the
SW_RESET register (Addr 0x10 in Bank 1).
Write to the standby mode polarity registers 0x0A to 0x0D
to set the proper polarities for the V-driver inputs, in order
to avoid damage to the CCD. See Table 35 for settings.
The V-driver supplies, VH and VL, can then be powered up
anytime after completing Step 3 to set the proper polarities.
By default, the AD9925 is in standby 3 mode. To place the
part into normal power operation, write 0x004 to the AFE
OPRMODE register (Addr 0x00 in Bank 1).
Write a 1 to the BANKSELECT register (Addr 0×7F)). This
will select Register Bank 2. Load Bank 2 registers with the
required VPAT group, vertical sequence, and field timing
information.
SUPPLIES
(OUTPUT)
(OUTPUT)
OUTPUTS
WRITES
DIGITAL
POWER
(INPUT)
SERIAL
(INPUT)
SYNC
CLI
VD
HD
0V
1
2
3
4
Figure 67. Recommended Power-Up Sequence and Synchronization, Master Mode
5
VDVDD = DVDD = DR
H1/H3, RG, DCLK
H2/H4
VH1 = VH2 = 15
VL = –7.5V
6
.0V
VDD = H
7
Rev. A | Page 52 of 96
VDD = RGVDD = TCVDD = A
8
9
7.
8.
9.
10. Configure the AD9925 for master mode timing by writing
11. Write a 1 to the OUT_CONTROL register (Addr 0x11 in
12. Generate a SYNC event: If SYNC is high at power-up,
Write a 0 to the BANKSELECT register to select Bank 1.
By default, the internal timing core is held in a reset state
with TGCORE_RSTB register = 0. Write a 1 to the
TGCORE_RSTB register (Addr 0x15 in Bank 1) to start the
internal timing core operation. Note: If a 2x clock is used
for the CLI input, the CLIDIVIDE register (Addr 0x30)
should be set to 1 before resetting the timing core.
Load the required registers to configure the high speed
timing, horizontal timing, and shutter timing information.
a 1 to the MASTER register (Addr 0x20 in Bank 1).
Bank 1).This will allow the outputs to become active after
the next SYNC rising edge.
bring the SYNC input low for a minimum of 100 ns. Then
bring SYNC back to high. This will cause the internal
counters to reset and will start the VD/HD operation. The
first VD/HD edge allows most Bank 1 register updates to
occur, including OUT_CONTROL to enable all outputs.
10
t
VDD = 3V
SYNC
11
12
1H
1ST FIELD
CLOCKS ACTIVE WHEN OUT_CONTROL
REGISTER IS UPDATED AT VD/HD EDGE
1V