AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 62

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9925
COMPLETE LISTING FO
All r
Table 37. AFE Register Map
A
00
01
02
03
Table 38. Miscellaneous Regist
Addres
0A
0B
0C
0D
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
E7
EB
F2
F3
F4
F5
F6
ddress
egister
s
s are V
Data Bit Content
[11:0]
[9:0]
[7:0]
[11:0]
Data B
[17:0]
[17:0]
[17:0]
[17:0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[11:0]
[0]
[23:0]
[0]
[0]
[0]
[2:0]
[3]
[5:4]
[6]
[7]
[8]
[3:0]
[0]
[11:0]
[12:0]
[11:0]
[12:0]
D updated, except where noted. L
it Content
er Map
Default Value
7
0
80
4
Defau
3FF8
3FF8
0
3FF8
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R REGISTER BANK 1
lt Value
Register Name
OPRMODE
VGAGAIN
CLAMPLEVEL
CTLMODE
Register Name
STBY1POL
STBY2POL
STBY3POL
OCONTPOL
SW_RST
OUTCONTROL
SYNCENABLE
SYNCPOL
SYNCSUSPEND
TGCORE_RSTB
OSC_PWRDOW
N
UNUSED
TEST
UPDATE
PREVENTUP-
DATE
MODE
UNUSED
OUTPUTPBLK
DVCMODE
INVERT_DCLK
SHUT_EXTRA
FG_TRIGEN
FG_TRIGPOL
FG_TRIGLIN1
FG_TRIGPIX1
FG_TRIGLIN2
FG_TRIGPIX2
ight gray cells
Rev. A | Page 62 of 96
= SCK
O
Register Description
AFE Operation Modes (See Table 45 for detail)
VGA Gain
AFE Control Modes (See Table 46 for detail)
Register Descri
Polarities for Output Signals during Standby 1 Mode.
Polarities for Output Signals during Standby 2 Mode.
Po
Polarities for Output Signals When OUTCONTROL = 0.
Software Reset. 1: Reset all registers to default, then self clear back
to 0.
O
Configures Pin 52 as a SYNC Input (= 1) or CLPOB/PBLK Output (= 0).
SYNC Active Polarity (0: Active Low).
Suspend Clocks during SYNC Active (1: Suspend).
Timing Core Reset Bar. 0: Reset TG Core, 1: Resume Operation.
CL
Set to 0.
Internal Use Only. Must be set to 0.
Se
Pr
MODE Register.
Set to 0.
Assigns Output for Pin 52 When Configured as Output.
0: CLPOB, 1: PBLK.
1: Enable DVC Mode. VD counter will reset every 2 fields, instead of
every field. VDLEN register should be programmed to the total num-
ber of lines contained in 2 fields, e.g., VDLEN = 525 lines will results
in 262.5 lines in each field.
1: Invert the DCLK Output.
Set to 0.
Selects FG_TRIG Signal to VSUB Pin (See Page 43).
Set to 0.
H3HBLKOFF, Set to 1 to Enable H3/H4 Outputs during HBLK (See
Page 19).
Set to 0.
Combines FG_TRIG and VSUB Signals (See Page 43).
FG_TRIG Signal Enable (See Page 43).
FG_TRIG Start Polarity.
FG_TRIG First Toggle Position, Line Location.
FG_TRIG First Toggle Position, Pixel Location.
FG_TRIG Second Toggle Position, Line Location.
FG_TRIG Second Toggle Position, Pixel Location.
ptical Black Clamp Leve
utput Control. 0: Make all outputs dc
events the update of the VD updated registers. 1: Prevent Update.
rial Update. Line (HD) in the field to update
updated, and dark gray cells = SG line updated.
larities for Output Signals during Standby 3 M
O Oscillator Power-Down (0: Oscillator Is Po
ption
inactive.
wered Down).
VD updated registers.
ode.