AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 21

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Increasing H-Clock Width during HBLK
The AD9925 will also allow the H1 to H4 pulse width to be
increased during the HBLK interval. The H-clock pu
can increase by reducing the H-clock frequency (see Figure 27).
T
register that allows the H-clock frequency to be reduced by 1/2,
1/4, 1/6, 1/8, 1/10, 1/12, or 1/14. The reduced frequen
only occur for H1 to H4 pulses that are located within t
H
Table 12. HBLK Width Register
Register
HBLKWIDTH
he HBLKWIDTH register, at Bank 1 Address 0x38, is a 3-bit
BLK area.
3 b
Length
H1/H3
H2/H4
HBLK
H1/H3
H2/H4
HBLK
Range
1 to 1/14
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS
TOG1
1/F
Description
Controls H1 to H4 widt
during HBLK as a frac-
tion of pixel rate
0: same frequency as
pixel rate
1: 1/2 pixel frequency,
i.e., doubles the H1 to H4
pulse width
2: 1/4 pixel frequency
3: 1/6 pixel frequency
4: 1/8 pixel frequency
5: 1/10 pixel frequency
6: 1/12 pixel frequency
7: 1/14 pixel frequency
PIX
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS
SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, OR 1/14 USING HBLKWIDTH REGISTER
Figure 27. Generating Wide H-Clock Pulses during HBLK Interval
Figure 26. Generating Special HBLK Patterns
lse width
cy will
TOG2
he
Rev. A | Page 21 of 96
2 × (1/F
TOG3
h
PIX
)
TOG4
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 28 shows an exampl CCD layout. The horizontal register
contains 28 d
from the CCD. In the vertical direction, there are 10 optical black
(OB) lines at the front of the readout and 2 at the back of the
readout. The horizontal direction has 4 OB pixels in the front
and 48 in the
Figure 29 shows the basic sequence layout to be used during the
effective pixel readout. The 48 OB pixels at the end of each
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval. The
HBLK, CLPOB, and PBLK parameters are programmed in the
vertical sequence registers.
More elaborate clamping schemes may be used, such as addin
in a separate sequence to clamp during the entire shield OB
lines. This requires configuring a separate vertical sequence for
reading out the OB lines.
TOG5
ummy pixels, which will occur on each line clocked
back.
TOG6
e
AD9925
line
g