AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 46

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AD9925BBCZ

Manufacturer Part Number
AD9925BBCZ
Description
IC CCD SIGNAL PROCESSOR 96CSPBGA
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 12-Bitr
Datasheet

Specifications of AD9925BBCZ

Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
96-CSPBGA
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Sample Rate
36MSPS
Input Voltage Range
0.8V
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Resolution
12b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-25C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
96
Package Type
CSPBGA
Number Of Channels
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9925BBCZ
Manufacturer:
AD
Quantity:
280
Part Number:
AD9925BBCZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
AD9925
ADC
The AD992
mized fo
(D
uses a 2 V in
for
AD
O
The optical black clamp loop is
in the signa
CCD’s black l
ter
black le
reg
255
r
in
turned on once per horizontal lin
more slowly
clamp
black clam
reg
stil
The CLPO
b
be at least 20 pixels wide. Shorter
the ability t
will b
sec
educe noise, and the correction value is applied to the ADC
lack pixels. It is recommended that the CLPOB pulse duration
ptical Black Clamp
put through a DAC. Normally, the optical black clamp loop is
NL) performan
val on each lin
l be used to pr
ister. The value can be programmed be
ister. When th
tion for timing examples.
typical linearit
9925.
LSB in 256 st
e reduced. Se
ing is used
vel referen
r high sp
ping m
B pulse should be placed durin
o track low freque
l chain and to track
5 uses high perfo
put r
to suit a particu
evel
e, th
eps. The r
during t
ovid
. During
e loo
ange
eed and
ay b
y a
ce
ce, s
e the H
is typically better than 0.5 LSB. The ADC
nd noise performanc
e ADC output is com
e programmable off
e disabled using Bit
. See Figure 10, Figu
p is disabled, the cla
elected by the user
he postprocessin
low power. Diff
orizontal Clam
the optical blac
esulting error
lar application. If external digital
rmance ADC architecture, opti-
ncy variations in the black level
used to remove residual offsets
low frequency variations in the
e, but this loop can be updated
pulse widths may be used, but
ping and Blank
signal is f
in the
set a
erential nonl
e plot
k (shielded) p
g th
D2 in
twee
g, the AD9925
mp l
re 12
pare
e CCD’s optical
djustment.
n 0 LSB and
evel register may
, and Figure 13
s for the
d with a fixed
clamp level
the OPRMODE
iltered to
inearity
ixel in-
ing
optical
Rev. A | Page 46 of 96
Digital Data Outputs
The AD9925
PHAS
ing is sh
lea
vali
CO
tr
by setting the AFE CONTROL Reg
The switchin
analog
om
edg
SH
but ex
D
lo
SHDLOC = 0, then DOUT PHAS
location of 12 or
the da
reg
The data output coding is normally straight binary, but the
c
CONTROL Register Bit D5 to a
oding may be changed to gray coding by setting the AFE
ansparent. The data outputs can also be disabled (three stated)
OUT PHASE location not occur between the SHD sampling
cation and 12 edges after the SHD location. For example, if
ve the output latc
P sampling locati
ister 0x03, Bit [4].
mended that the
d immediately fr
NTROL Register
e as the SHP sam
E register valu
perimentation
ta outputs, the output latch
signal path. T
own in Figu
g of the data out
digital output da
greater. If adjustable phase is not required for
on. O
hes
re 2
om
e, as sho
DO
o minimi
plin
Bit D4
is n
transparent, so that t
1 and Figure 22. It is
the ADC. Programm
UT PHASE register
g location, or up to
ecessary. It is recommended that the
ther settings can pr
to a 1 will set th
wn in Figure 55
puts can couple noise back to the
ze any switchi
ta is latched using the DOUT
1.
E should be set to an edge
can be left tr
ister Bit D3 to a 1.
e out
ng noise, it is r
oduc
be se
12 edg
. Output data t
he d
also
ing
ansparent using
put latches
ata outputs are
the AFE
e good results,
t to the same
possible to
es after the
ec-
im-

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