AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 61

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Updating New Register Values
The AD99 5’s internal register are updated at d
depe
four differe
1.
2.
Tab
Update Type
SCK Update
VD Update
SG Line Up
SCP Update
le 36. R
nding
SCK U
as soo
ters, sh
functi
bounda
select r
SCK u
VD U
field r
edge. B
current field will not be corrupted, and the new register
values will be applied to the next field. Bank 1 register up-
dates may be further delayed past the
using the UPDATE registe (Addr 0x19). Th will delay
VD up
field registers are not affected by the UPDATE register.
XV1 TO XV6
2
ons that d
pdated: M
egister
d
n as the 24t
dated
on t
pdated
nt ty
dates t
d
d
pda
aded in
egister (
egiste
y up
SERIAL
ry, such
WRITE
XSG
he particular reg
HD
VD
ted: Some of the registers in Bank 1
pes of register u
dating these val
s in Bank 2, ar
o any HD line
r Update Loca
.
gray in the B
Addr 0x7F i
Register Bank
Bank 1 Only
Bank 1, Bank
Bank 1 Only
Bank 2, Bank
o not requi
as power-up
ost of the r
h data bit
s
r
e up
pda
re gati
n Ban
ister
ues
egisters in B
in th
(D23
tio
ank 1 r
2
3
and r
tes:
ns
dated at the nex
at the next VD
UPDATED
. Table 36 summ
e field. Note th
) is written. T
k 1 and Bank
ng with the n
SCK
eset functions. T
egister list, a
Description
Register is immediately updated
Register is updated at the VD falli
by using the UP
UPDATE reg
Register is u
Register is u
SCP 0
Figure 77. R
VD falling edge by
ank 1,
USE VSEQ2
UPDAT
REGION 0
VD
iffe
is
as well as the
ED
hese regis-
at the Bank
ext VD
edge, the
egister Update Loca
rent times,
2) is also
ister.
pdated at the
pdated at th
t VD falling
are update
re used for
arizes the
SCP 1
DATE register at
he bank
UPDATED
SGLINE
USE VSEQ3
REGION 1
SG
Rev. A | Page 61 of 96
d
2
e next SC
HD falli
SCP 2
tions (
UPD
S
Addr 0x19 in Ba
when the 24
ng edge. VD updated registers in Bank 1 may be delayed further
ng edge at the end of the SG active l
CP
ATED
P when the register will be u
See Table 40 for Definitions)
3.
4.
USE VSEQ5
REGION 2
SG Line Updated: A few of the registers in Bank 1 are up-
dated at the end o
edge. These registers control t
SUBCK output will not upda
been completed. These regist
Bank 1 register list.
SCP Updated: In Bank 2 an
pattern group and vertical s
through Addr 0xCF, exclud
the next SCP, where they w
Figure 77, this field has sele
Sequence 3 for the vertical
to any of the Vertical Sequence 3 registers, or any of the ver-
tical pattern group registers that are referenced by Vertical
Sequence 3, will be updated at SCP1. If multiple writes are
done to the same register, the last one done before SCP1
will be the one that is updated. Likewise, register writes to
any Vertical Sequence 5 registers will be updated at SCP2,
and register writes t
be updated at SCP3.
th
data bit (D23) is clocked in.
nk 1. Bank 2 updates will not be affected by th
SCP 3
USE VSEQ8
f the SG active line, at the HD falling
REGIO
o any Vertical Sequence 8 registers will
sed.
N 3
SCP 0
ill be used. For example, in
outputs. This means that a write
ing Addr 0×7F) are updated at
cted Region 1 to use Vertical
equence registers (Addr 0x00
d Bank 3, all of the vertical
te until after the SG line has
ers are crosshatched in the
he SUBCK signal, so that the
ine.
AD9925
e