AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 45

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

ANALOG FRONT END DESCRIPTION
AND OPERATION
The AD9925 signal processing chain is shown in Figure 55.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc-
restore circuit is used with an external 0.1 µF series coupling
capacitor. This restores the dc level of the CCD signal to ap-
proximately 1.3 V, which allows it to be compatible with the
3 V supply voltage of the AD9925.
Correlated Double Sampler
T
video information and reject the low frequency noise. The timing
shown in Figure 19 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference level
and data level of the CCD signal, respectively. The placement of
the SHP and SHD sampling edges is determined by setting the
SAMPCONTROL register located at Addr 0x36. Placement of
these two clock signals is critical in achieving the best perform-
ance from the CCD.
he CDS circuit samples each CCD pixel twice to extract the
0.1µF
CCDIN
CLI
DC RESTORE
1.3V
SHP
SHP
CDS
GENERATION
PRECISION
SHD
TIMING
SHD
PHASE
DOUT
REGISTER
VGA GAIN
Figure 55. Analog Front End Functional Block Diagram
CLPOB
6dB ~ 42dB
GENERATION
VGA
TIMING
V-H
PBLK
Rev. A | Page 45 of 96
DAC
DIGITAL
FILTER
OPTICAL BLACK
Variable Gain Amplifier
The VGA stage provides a gain range of 6 dB to 42 dB, program-
mable with 10-bit resolution through the serial digital interface.
The minimum gain of 6 dB is needed to match a 1 V input signal
with the ADC full-scale range of 2 V. When compared to 1 V full-
scale systems, the equivalent gain range is 0 dB to 36 dB.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
where the Code r
INTERNAL
CLAMP
Gain (dB) = (0.0351 × Code) + 6 dB
1.0µF 1.0µF
REFB
1.0V
12-BIT
V
ADC
REF
42
36
30
24
18
12
6
2V FULL SCALE
0
REFT
2.0V
CLAMP LEVEL
DOUT PHASE
127
REGISTER
CLI
ange is 0 to 1023.
8
255
CLPOB
Figure 56. VGA Gain Curve
AD9925
VGA GAIN REGISTER CODE
OUTPUT
DELAY
LATCH
FIXED
DOUT
DATA
DLY
383
PBLK
511
MODE
DCLK
1
0
12
639
DCLK
DOUT
767
895
AD9925
1023