AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 63

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 39. VD/HD Register Map
Address
20
21
22
23
Table 40. Timing Core Register Map
Address
30
31
32
33
34
35
36
37
38
Table 41. CLPOB Masking Register Map
Address
40
41
42
43
Data Bit Content
[0]
[0]
[11:0]
[17:12]
[11:0]
Data Bit Content
[0]
[0]
[6:1]
[12:7]
[0]
[6:1]
[12:7]
[0]
[6:1]
[12:7]
[0]
[1]
[2:0]
[5:3]
[8:6]
[11:9]
[14:12]
[5:0]
[11:6]
[5:0]
[6]
[8:7]
[2:0]
Data Bit Content
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[11:0]
[12]
Default Value
0
0
0
0
0
Default Value
0
1
0
20
1
0
20
1
0
20
0
0
1
1
1
1
1
24
0
0
0
2
0
Default Value
FFF
FFF
FFF
FFF
FFF
FFF
0
SCP0
CLPMASK4
Register Name
MASTER
VDHDPOL
HDRISE
VDRISE
Register Name
CLIDIVIDE
H1POL
H1POSLOC
H1NEGLOC
H3POL
H3POSLOC
H3NEGLOC
RGPOL
RGPOSLOC
RGNEGLOC
H1RETIME
H3RETIME
H1DRV
H2DRV
H3DRV
H4DRV
RGDRV
SHPLOC
SHDLOC
DOUTPHASE
DCLKMODE
DOUTDLY
HBLKWIDTH
Register Name
CLPMASK0
CLPMASK1
CLPMASK2
CLPMASK3
CLPMASK5
CLPMASKTYPE
Rev. A | Page 63 of 96
Register Description
VD/HD Master or Slave Timing (0 = Slave Mode).
VD/HD Active Polarity. 0 = Low and 1 = High.
Rising Edge Location for HD.
Rising Edge Location fo
SCP0. Used for All Fields.
Register Description
Divide CLI Input Clock by 2. 1 = Divide by 2.
H1 Polarity. 0: Inversion, 1: No Inversion.
H1 Positive Edge Location.
H1 Negative Edge Location.
H3 Polarity. 0: Inversion, 1: No Inversion.
H3 Positive Edge Location.
H3 Negative Edge Location.
RG Polarity. 0: Inversion, 1: No Inversion.
RG Positive Edge Location.
RG Negative Edge Location.
Retime H1/H3 HBLK to Internal H1/H3 Clocks. Preferred setting is 1
for each bit, which adds one cycle of delay to the programmed HBLK
toggle positions.
Drive Strength Control for H1.
0: Off.
1: 4.3 mA.
2: 8.6 mA.
3: 12.9 mA.
4: 17.2 mA.
5: 21.5 mA.
6: 25.8 mA.
7: 30.1 mA.
Drive Strength Control for H2 (Same Values as H1DRV).
Drive Strength Control for H3 (Same Values as H1DRV).
Drive Strength Control for H4 (Same Values as H1DRV).
Drive Strength Control for RG (Same Values as H1DRV).
SHP Sampling Location.
SHD Sampling Location.
DOUT Phase Control.
0: DCLK Tracks DOUTPHASE.
1: DCLK Does Not Track DOUTPHASE, Remains Fixed with Regards to
CLI
Data Output Delay (t
0: No Delay, 1: ~4 ns, 2: ~8 ns, and 3: ~12 ns.
Controls HBLK Width as a Fraction of H1 to H4 Frequency.
0: same, 1: 1/2, 2: 1/4, 3: 1/6, 4: 1/8, 5: 1/10, 6: 1/12, and 7: 1/14.
Register Description
CLPOB Line Masking Line No. 0, or Mask0 Range, Start Line
CLPOB Line Masking Line No. 1, or Mask0 Range, End Line
CLPOB Line Masking Line No. 2, or Mask1 Range, Start Line
CLPOB Line Masking Line No. 3, or Mask1 Range, End Line
CLPOB Line Masking Line No. 4, or Mask2 Range, Start Line
CLPOB Line Masking Line No. 5, or Mask2 Range, End Line
0: CLPOB Line Masking, 1: Enable CLPOB Range Masking
OD
) with Respect to DCLK.
r VD.
AD9925