AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 53

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

Table 33. Power-Up Register Write Sequence
Address
0x10
0x0A to 0x0D
0x00
0x7F
0x00 to 0xFF
0x7F
0x15
0x31 to 0x71
0x20
0x11
0x13
Generating Software SYN
If an exte
ate an i
register (
SYNC inp
After power-up, follow the same procedure as before, for Steps 1
through 11. Then, for Step 12, instead of using the external
SYNC pulse, write a 1 to the SYNCPOL register. This will gen-
erate the SYNC internally, and the timing operation will begin.
SYNC during Master Mode Operation
T
resync the AD9925 counters with external timing, as shown in
Figure 68. The operation of the digital outputs may be suspended
during the SYNC operation by setting the SYNCSUSPEND regis-
ter (Addr 0x14) to a 1.
Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same
as the procedure described for master mode operation, with
two exceptions:
1.
2.
he SYNC input may be used any time during operation to
Eliminate Step 10. Do not write the part into master mode.
No SYNC pulse is required in slave mode. Substitute Step
12 with starting the external VD and HD signals. This will
synchronize the part, allow the Bank 1 register updates,
and start the timing operation.
nternal SYNC in the AD9925 by writing to the SY
rnal SYNC pulse is
Addr 0x13). If the
ut (Pin J5) should
Data
0x01
TBD
0x04
0x01
TBD
0x00
0x01
TBD
0x01
0x01
0x01
De
Re
Standby V-Driver Input Signal Polarities
Power-Up the AFE and CLO Oscillator
Select Register Bank 2
VP
Tim
Select Register Bank 1
Reset Internal Timing Core
Ho
Configure for Master Mode
Enable All Outputs after SYNC
SYNCPOL (for Software SYNC Only)
softwa
set All
AT, Ve
rizonta
not av
scription
C with
be tie
ing
rtical Sequence, and Fi
ailable, it is possible to
re SYNC option is use
d to ground (VSS).
Registers to Default Va
l and Shutter Timing
out External SYNC
NCPO
Signal
d, the
eld
gener-
lues
Rev. A | Page 53 of 96
L
When the AD9925 is used in slave m
puts a
falling edg
(CLI) after
reset. The r
Vertical T
One addit
counters is
ternal coun
toggle posi
For master
should not
SUBCK, H
Figure 71
restriction
and canno
delayed wi
ited area is
Additional Considerations for Toggle Positions
In addition to avoiding toggle position placement near the counter-
reset location, there are a couple of other recommendations.
Pixel location 0 should not be used for any of the toggle positions
for the XSG and SUBCK pulses.
Also, the propagation delay of the V-driver circuit should be con-
sidered when programming the toggle positions for the XV, XSG,
and SUBCK pulses. The delay of the V-driver circuit is specified
in Table 3 and is a maximum of 200 ns.
re us
ional co
shows t
e of VD
t be us
th resp
tions sh
applies:
ed to synchro
eset op
oggle Position Plac
BLK, P
differe
the fa
the ver
ters ar
mode,
be use
lling edge of HD until t
ed. However, in slave m
ect to VD/HD placem
e reset, there is an area
d for toggle position pl
he same example for sl
nt than it is in master
eration is shown in Fig
nsideration during th
, there will be a latenc
BLK, or CLPOB puls
tical toggle position pl
the last 18 pixels befo
ould be programmed
the last 18 pixels befo
nize the intern
emen
ode, the VD and HD in-
es (see Fig
e reset o
re the H
mode.
t near
ent; th
y of 23
ure 69
al counters. F
.
he int
aceme
ave mo
re the
aceme
of 18 pixe
ode, t
ernal H-Counter is
.
erefore, the inhib-
he counter reset is
counters are reset
nt. Before the in-
nt of the XV, XSG,
Counter Reset
master clock edges
f the internal
de. The same
D falling edge
ure 70).
ls where no
ollowing a
AD9925