AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 16

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9925
Figure 20 sho
speed clo
H-Driver and
In addition to the p
features on-chip o
puts. These driv
C
o
D
each output is adjustable in 4.1 mA increments, with the mini-
mum setting of 0 equal to OFF or three-state and the
s
As shown in Figure 18, Figure 19, and Figure
outputs are
cr
cro
Table 8. Timing Core Register Parameters for H1, H3, RG, SHP/SHD
P
Polarity
Positive Edge
Negative Edge
Sampling Location
Drive Strength
etting of 7 equal to 30.1 mA.
ptimum rise/fall time with a particular load by using the
arameter
CD inputs. The H-driver and RG current can be adjusted for
RVCONTROL register (Addr x35). The 3-bit drive setting for
ossover voltage is approximately
ssover voltage is not programm
ck signals.
inverses of H1 and H3,
ws the de
RG Out
ers are p
SIGNAL
PROGRAMMABLE CLOCK POSITIONS:
1. RG RISING EDGE.
2. RG FALLING EDGE.
3. SHP SAMPLE LOCATION.
4. SHD SAMPLE LOCATION.
5. H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1).
7. H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 I
u
rogra mable timing posi
tpu
CCD
RG
H1
H2
H3
H4
t dri
fault timi
Length
1 b
6 b
6 b
6 b
3 b
puts
ow
m
1
5
vers for the RG
erful enough to
7
ng locatio
2
able.
50% of th
respectively. The H1/H
3
6
ns for all
Range
High/Low
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Edge Location
0 to 47 Current Steps
and H1 to H4 out-
directly drive the
e output swing. The
tions, the AD9925
20, the H2 and H4
8
Figure 18. High Speed Clock Programmable Locations
of the high
maximum
4
2
Rev. A | Page 16 of 96
Description
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Negative Edge Location for H1, H3, and RG
Sampling Location for Internal SHP and SHD Signals
Drive Current for H1 to H4 and RG Outputs (4.1 mA per Step)
S INVERSE OF H3).
Digital Da
The AD9925 data output and DCLK phase are programmable
using the DOUTPHASE register (Addr
edge from 0 to 47 may be programmed, a
Normally, the DOUT and DCLK signals will track
based on the DOUTPHASE register contents. The DCLK o
put phase can also be held fixed with respect to the data outputs
by changing the DCLKMODE register high (Addr x37, Bit [6]).
In this mode, the DCLK output will remain at a fixed phase
equal to CLO (the inverse of CLI), while the data output phase
is still programmable.
There is a fixed output delay from the DCLK rising edge to the
DOUT transition, called t
four values between 0 ns and 12 ns by using the DOUTDELAY
register (Addr x37,
The pi
After t
delay u
peline delay through the
he CCD input is sampled
ntil the data is available.
ta Outputs
Bits [8:7]). T
OD
. This delay can be programmed to
AD9925 is shown in
he default value is 8 ns
by SHD, there is an
x37, Bits [5:0]). Any
s shown in Figure 21.
in phase,
11 cycle
Figure 22.
.
ut-