AD9925BBCZ Analog Devices Inc, AD9925BBCZ Datasheet - Page 60

• Manufacturer Part Number: AD9925BBCZ
• Description: IC CCD SIGNAL PROCESSOR 96CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 12-Bitr

Specifications of AD9925BBCZ

• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 96-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 36MSPS
• Input Voltage Range: 0.8V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -25C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 96
• Package Type: CSPBGA
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant

AD9925
Register Address BANK 1, BANK
The AD99 5 address space is d vided into three
ter b
Regi
divid
with the AD
ters for
ti
tions. Register Bank 2 contains all of the
vertical pattern groups, vertical sequences, and fi
Regi
XV8
support ne
When
which addr
data value
writ
ming core, CLPOB masking, VSG patterns, and shutter func-
ten. To
ster Ba
ster Ba
anks, r
functi
ed. Re
ADDR
ADDR
ADDR 0x8F
ADDR 0x00
ADDR
ADDR 0x20
ADDR 0x30
ADDR 0x40
ADDR 0x50
ADDR 0x60
writ
the
2
of 0 is w
wer CC
nk 3
onali
ing to
eferr
nk 3
gister B
0xFF
AFE, m
ess ban
0x7F
write t
0x10
9995 re
. Figure 76 illust
contains new reg
ty. These additio
ed to as Register
the AD9925, A
o Bank 3, a da
Ds that requir
k is being writ
ank 1 and Ba
ritten. To wri
iscellaneous
MISCELLANEOUS REGISTERS
gisters. Regi
REGISTER BANK 2, BANK 3
VSG PATTERN REGISTERS
CLPOB MASK REGISTERS
INVALID, DO NOT ACCESS
TIMING CORE REGISTERS
REGISTER BANK 1
SHUTTER REGISTERS
VD/HD REGISTERS
AFE REGISTERS
SWITCH TO
i
rate
ster
fun
nal
nk 2 a
te to
ta v
ddr
isters fo
e 8
ten to
Ba
ctions, VD/HD
-phases of verti
nk 1, Register B
outputs allow th
s how the three
alue of 2 is writ
2, and BANK 3
Bank 1 contain
0x7F is used to
Bank 2, a data
re backward
. To write to
r accessing
information for the
Figure 76.
ADD
ADD
ADDR 0x7E
ADD
ADDR 0x00
ADDR 0x7F
ADDR 0x80
eld i
dif
W
cal clocking.
compatib
R 0xCF
R 0xD0
Layout of Internal
the XV7 and
ten.
R 0xFF
ferent regis-
s the regi
Bank 1, a
ank 2, and
parame
e AD992
banks are
value of 1 is
RITE TO ADDR
nformation.
specify
ters,
FIE
5 to
VSEQ0 TO VSEQ9 REGISTERS
le
s-
Rev. A | Page 60 of 96
VPAT0 TO VPAT9 REGISTERS
REGISTER B
LD 0 TO FI
ESS 0x7F
XV1 TO X
REGISTE
XV1 TO X
Regi
SWI
ster Bank 1, Bank 2, and Bank 3
FOR
TCH TO
FOR
ELD 5 REGISTERS
ANK 1, BANK 3
R BANK 2
V6 SIGNALS
V6 SIGNALS
TO SWITCH REGISTER BANKS
Note that Register Bank 1 contains many unused addresses.
Undefined addresse
considered Don’t Cares, and it is acceptable if
are filled in with all 0s during a continuous
tion. However, the undefin
written to, or the AD9925
tions are the FG_TRIG
0xF6, which may be written as specified on Page 43.
Default values for Register Bank 2 and Bank 3 are undefined after
power-up. Appropri
ter banks to ensure proper operation. In ap
XV7 and XV8 signals are not used, the
still be programmed with
able behavior in the V-dri
ADDR 0x4F
ADDR 0x7F
ADDR 0xF
ADDR 0x00
ADDR 0x50
ADDR 0x77
ate values should be written into these regis-
s between Addr 0x00 and Addr 0x7F are
F
registers 0xE7, 0xEB, and 0xF2 through
ver circuit.
known values to prevent unpredict-
may not operate properly. The excep-
ed addresses above 0x7F must not be
VSEQ0 TO VSEQ9 REGISTERS
VPAT0 TO VPAT9 REGISTERS
REGISTER BANK 2, BANK 3
INVALID, DO NOT ACCESS
REGISTER BANK 3
XV7, XV8 SIGNALS
XV7, XV8 SIGNALS
SWITCH TO
FOR
FOR
Bank 3 registers should
plications where the
register write opera-
these addresses