AD9888KSZ-140 Analog Devices Inc, AD9888KSZ-140 Datasheet - Page 11

• Manufacturer Part Number: AD9888KSZ-140
• Description: IC FLAT PANEL INTERFACE 128-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9888KSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: 2-Wire Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-MQFP, 128-PQFP
• Mounting Type: Surface Mount
• Supply Current: 200mA
• Power Dissipation Pd: 850mW
• Supply Voltage Range: 3V To 3.6V, 2.2V To 3.6V
• Digital Ic Case Style: MQFP
• No. Of Pins: 128
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC
• Number Of Elements: 3
• Resolution: 8Bit
• Sample Rate: 140MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±0.25/±0.5V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.05W
• Differential Linearity Error: ±1.35LSB
• Integral Nonlinearity Error: ±2.5LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: MQFP
• Input Signal Type: Single-Ended
• Interface Type: 2-wire, Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Four programmable registers are provided to optimize the
performance of the PLL. These registers are:
1. The 12-Bit Divisor Registers. The input Hsync frequencies
2. The 2-Bit VCO Range Register. To lower the sensitivity of
Standard
VGA
SVGA
XGA
SXGA
UXGA
QXGA
*Graphics sampled at 1/2 the incoming pixel rate using Alternate Pixel Sampling mode.
REV. B
range from 15 kHz to 110 kHz. The PLL multiplies the fre-
quency of the Hsync signal, producing pixel clock frequencies
in the range of 10 MHz to 205 MHz. The Divisor Register
controls the exact multiplication factor. This register may be
set to any value between 221 and 4095. (The divide ratio that
is actually used is the programmed divide ratio plus one.)
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range Register sets this operating range.
Because there are only four possible regions, only the two
least significant bits of the VCO Range Register are used.
The frequency ranges for the lowest and highest regions are
shown in Table II.
Table IV. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Figure 6. PLL Loop Filter Detail
Resolution
640
800
1024
1280
1600
2048
2048
0.0039 F
C
480
600
P
768
1024
1200
1536
1536
FILT
Rate (Hz)
Refresh
60
72
75
85
56
60
72
75
85
60
70
75
80
85
60
75
85
60
65
70
75
85
60
75
R
3.3k
0.039 F
C
Z
Z
PV
D
Horizontal
Frequency (kHz)
31.5
37.7
37.5
43.3
35.1
37.9
48.1
46.9
53.7
48.4
56.5
60.0
64.0
68.3
64.0
80.0
91.1
75.0
81.3
87.5
93.8
106.3
–11–
3. The 3-Bit Charge Pump Current Register. This register
PV1
0
0
1
1
allows the current that drives the low-pass loop filter to be
varied. The possible current values are listed in Table III.
Table III. Charge Pump Current/Control Bits
Pixel Rate (MHz)
25.175
31.500
31.500
36.000
36.000
40.000
50.000
49.500
56.250
65.000
75.000
78.750
85.500
94.500
108.000
135.000
157.500
162.000
175.500
189.000
202.500
229.500*
260.000*
315.000*
Ip2
0
0
0
0
1
1
1
1
PV0
0
1
0
1
Table II. VCO Frequency Ranges
Ip1
0
0
1
1
0
0
1
1
Pixel Clock Range
(MHz)
10–41
41–82
82–150
150+
Ip0
0
1
0
1
0
1
0
1
VCORNGE
00
00
00
00
00
00
01
01
01
01
01
01
10
10
10
10
11
11
11
11
11
10
11
11
Current ( A)
50
100
150
250
350
500
750
1500
AD9888
K
(MHz/V)
150
150
150
180
010
100
100
100
100
101
011
011
011
100
100
101
011
011
011
100
100
100
100
101
101
110
100
100
Current
VCO
Gain