AD9888KSZ-140 Analog Devices Inc, AD9888KSZ-140 Datasheet - Page 21

• Manufacturer Part Number: AD9888KSZ-140
• Description: IC FLAT PANEL INTERFACE 128-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9888KSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: 2-Wire Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-MQFP, 128-PQFP
• Mounting Type: Surface Mount
• Supply Current: 200mA
• Power Dissipation Pd: 850mW
• Supply Voltage Range: 3V To 3.6V, 2.2V To 3.6V
• Digital Ic Case Style: MQFP
• No. Of Pins: 128
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC
• Number Of Elements: 3
• Resolution: 8Bit
• Sample Rate: 140MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±0.25/±0.5V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.05W
• Differential Linearity Error: ±1.35LSB
• Integral Nonlinearity Error: ±2.5LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: MQFP
• Input Signal Type: Single-Ended
• Interface Type: 2-wire, Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

HSYNC PULSEWIDTH
07
INPUT GAIN
08
09
0A
INPUT OFFSET
0B
0C
REV. B
be programmed to any value between 1 and 255. A value
of 0 is not supported.
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufficient clamp-
ing time can produce brightness changes at the top of the
screen, and a slow recovery from large changes in the
Average Picture Level (APL), or brightness.
When the external clamp control bit is set to 1, this regis-
ter is ignored.
7-0
An 8-bit register that sets the duration of the Hsync
output pulse.
The leading edge of the Hsync output is triggered by the
internally generated, phase adjusted PLL feedback clock.
The AD9888 then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase adjusted.
7-0
An 8-bit word that sets the gain of the RED channel.
The AD9888 can accommodate input signals with a
full-scale range of between 0.5 V and 1.0 V p-p. Setting
REDGAIN to 255 corresponds to an input range
of 1.0 V. A REDGAIN of 0 establishes an input range
of 0.5 V. Note that increasing REDGAIN results in the
picture having less contrast (the input signal uses fewer
of the available converter codes). See Figure 2.
7-0
An 8-bit word that sets the gain of the GREEN channel.
See REDGAIN (08).
7-0
An 8-bit word that sets the gain of the BLUE channel.
See REDGAIN (08).
7-1
A 7-bit offset binary word that sets the dc offset of the
RED channel. One LSB of offset adjustment equals
approximately one LSB change in the ADC offset.
Therefore, the absolute magnitude of the offset adjustment
scales as the gain of the channel is changed. A nominal
setting of 63 results in the channel nominally clamping
the back porch (during the clamping interval) to code 00.
An offset setting of 127 results in the channel clamping to
code 64 of the ADC. An offset setting of 0 clamps to code
–63 (off the bottom of the range). Increasing the value of
Red Offset decreases the brightness of the channel.
7-1
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
Hsync Output Pulsewidth
Red Channel Gain Adjust
Green Channel Gain Adjust
Blue Channel Gain Adjust
Red Channel Offset Adjust
Green Channel Offset Adjust
–21–
0D
0E
0E
0E
0E
Override Bit
0
1
Table VIII. Hsync Input Polarity Override Settings
7-1
A 7-bit offset binary word that sets the dc offset of the
BLUE channel. See REDOFST (0B).
7
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into the PLL.
The default for Hsync polarity override is 0 (polarity
determined by chip).
6
A bit that must be set to indicate the polarity of the Hsync
signal that is applied to the PLL Hsync input.
Active Low means the leading edge of the Hsync pulse
is negative-going. All timing is based on the leading edge
of Hsync, which is the falling edge. The rising edge has
no effect.
Active High means the leading edge of the Hsync pulse
is positive-going. This means that timing will be based on
the leading edge of Hsync, which is now the rising edge.
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
Clamp Placement (Register 05H), will not be placed as
expected, which may generate clamping errors.
The power-up default value is HSPOL = 1.
5
One bit that determines the polarity of the Hsync output
and the SOG output. Table X shows the effect of this
option. SYNC indicates the logic state of the sync pulse.
The default setting for this register is 0.
4
This bit is used to override the automatic Hsync selection.
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
Table X. Hsync Output Polarity Settings
Table IX. Hsync Input Polarity Settings
Blue Channel Offset Adjust
Hsync Input Polarity Override
HSPOL
Hsync Output Polarity
Setting
0
1
Active Hsync Override
HSPOL
0
1
Result
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
SYNC
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
Hsync Input Polarity
Function
Active Low
Active High
AD9888