AD9888KSZ-140 Analog Devices Inc, AD9888KSZ-140 Datasheet - Page 23

• Manufacturer Part Number: AD9888KSZ-140
• Description: IC FLAT PANEL INTERFACE 128-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9888KSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: 2-Wire Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-MQFP, 128-PQFP
• Mounting Type: Surface Mount
• Supply Current: 200mA
• Power Dissipation Pd: 850mW
• Supply Voltage Range: 3V To 3.6V, 2.2V To 3.6V
• Digital Ic Case Style: MQFP
• No. Of Pins: 128
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC
• Number Of Elements: 3
• Resolution: 8Bit
• Sample Rate: 140MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±0.25/±0.5V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.05W
• Differential Linearity Error: ±1.35LSB
• Integral Nonlinearity Error: ±2.5LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: MQFP
• Input Signal Type: Single-Ended
• Interface Type: 2-wire, Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. B
0F
0F
0F
10
3
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is low, and continue
operating at the same nominal frequency until COAST
goes high.
Active High means that the clock generator will ignore
Hsync inputs when COAST is high, and continue
operating at the same nominal frequency until COAST
goes low.
This function needs to be used along with the COAST
polarity override bit (Bit 4).
The power-up default value is CSTPOL = 1.
2
This bit is used to either allow or disallow the low power
mode. The low power mode (seek mode) occurs when
there are no signals on any of the Sync inputs.
The default for this register is 1.
1
This bit is used to put the chip in power-down mode. In
this mode, the chip’s power dissipation is reduced to a
fraction of the typical power (see the Electrical Character-
istics table for exact power dissipation). When in power-
down, the HSOUT, VSOUT, DATACK, DATACK, and
all 48 of the data outputs are put into a high impedance
state. (Note: the SOGOUT output is not put into high
impedance.) Circuit blocks that continue to be active
during power-down include the voltage references, sync
processing, sync detection, and the serial register. These
blocks facilitate a fast startup from power-down.
The default for this register is 1.
7-3
This register allows the comparator threshold of the Sync-
on-Green slicer to be adjusted. This register adjusts it in
Table XX. COAST Input Polarity Settings
Table XXI. Seek Mode Override Settings
COAST Input Polarity
Seek Mode Override
PWRDN
Sync-on-Green Slicer Threshold
Select
1
0
Table XXII. Power-Down Settings
Select
0
1
CSTPOL
0
1
Result
Allow Seek Mode
Disallow Seek Mode
Result
Power-Down
Normal Operation
Function
Active Low
Active High
–23–
10
10
11
12
13
steps of 10 mV, with the minimum setting equal to 10 mV
and the maximum setting equal to 330 mV.
The default setting is 15 and corresponds to a threshold
value of 0.16 V.
2
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three chan-
nels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 9.
The default setting for this register is 0.
1
A bit that determines whether the blue channel is clamped
to ground or to midscale. Clamping to midscale actually
clamps to Pin 24.
The default setting for this register is 0.
7:0
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or low.
It works like a low-pass filter to ignore Hsync pulses in order
to extract the Vsync signal. This register should be set to
some number greater than the maximum Hsync pulsewidth.
Note: the sync separator threshold uses an internal dedicated
clock with a frequency of approximately 5 MHz.
The default for this register is 32.
7-0
This register allows the COAST signal to be applied prior
to the Vsync signal. This is necessary in cases where pre-
equalization pulses are present. The step size for this
control is one Hsync period.
The default is 0.
7-0
This register allows the COAST signal to be applied
following to the Vsync signal. This is necessary in cases
where post-equalization pulses are present. The step size
for this control is one Hsync period.
The default is 0.
Clamp
0
1
Clamp
0
1
Table XXIV. Blue Clamp Select Settings
Table XXIII. Red Clamp Select Settings
Red Clamp Select
Blue Clamp Select
Sync Separator Threshold
Pre-COAST
Post-COAST
Function
Clamp to Ground
Clamp to Midscale (Pin 9)
Function
Clamp to Ground
Clamp to Midscale (Pin 24)
AD9888