AD9888KSZ-140 Analog Devices Inc, AD9888KSZ-140 Datasheet - Page 20

• Manufacturer Part Number: AD9888KSZ-140
• Description: IC FLAT PANEL INTERFACE 128-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9888KSZ-140

• Applications: Graphic Cards, VGA Interfaces
• Interface: 2-Wire Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-MQFP, 128-PQFP
• Mounting Type: Surface Mount
• Supply Current: 200mA
• Power Dissipation Pd: 850mW
• Supply Voltage Range: 3V To 3.6V, 2.2V To 3.6V
• Digital Ic Case Style: MQFP
• No. Of Pins: 128
• Operating Temperature Range: 0°C To +70°C
• Svhc: No SVHC
• Number Of Elements: 3
• Resolution: 8Bit
• Sample Rate: 140MSPS
• Input Polarity: Bipolar
• Input Type: Voltage
• Rated Input Volt: ±0.25/±0.5V
• Differential Input: No
• Power Supply Requirement: Single
• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3V
• Single Supply Voltage (max): 3.6V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Power Dissipation: 1.05W
• Differential Linearity Error: ±1.35LSB
• Integral Nonlinearity Error: ±2.5LSB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 128
• Package Type: MQFP
• Input Signal Type: Single-Ended
• Interface Type: 2-wire, Serial
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AD9888
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00
PLL DIVIDER CONTROL
01
02
CLOCK GENERATOR CONTROL
03
7-0
An 8-bit register that represents the silicon revision.
Revision 0 = 0000 0000, Revision 1 = 0000 0001.
7-0
The eight most significant bits of the 12-bit PLL
divide ratio PLLDIV. (The operational divide ratio is
PLLDIV + 1.)
The PLL derives a master clock from an incoming Hsync
signal. The master clock frequency is then divided by an
integer value, such that the output is phase-locked to
Hsync. This PLLDIV value determines the number of pixel
times (pixels plus horizontal blanking overhead) per line.
This is typically 20% to 30% more than the number of
active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios
from 2 to 4095. The higher the value loaded in this
register, the higher the resulting clock frequency with
respect to a fixed Hsync frequency.
VESA has established standard timing specifications that
will assist in determining the value for PLLDIV as a
function of horizontal and vertical display resolution
and frame rate (Table IV).
However, many computer systems do not conform precisely
to the recommendations, and these numbers should be
used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH).
The AD9888 updates the full divide ratio only when the
LSBs are changed. Writing to this register by itself will
not trigger an update.
7-4
The four least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69H, PLLDIVL = DxH).
The AD9888 updates the full divide ratio only when this
register is written to.
7-6
Two bits that establish the operating range of the clock
generator.
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
The PLL gives the best jitter performance at high fre-
quencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actually
operates at a higher frequency but then divides down the
clock rate afterwards. Table VI shows the pixel rates for
each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
Chip Revision
PLL Divide Ratio MSBs
PLL Divide Ratio LSBs
VCO Range Select
–20–
The power-up default value is 01.
03
04
CLAMP TIMING
05
06
5-3
Three bits that establish the current driving the loop filter
in the clock generator.
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
7-3
A 5-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25° shift
in sampling phase.
The power-up default value is 16.
7-0
An 8-bit register that sets the position of the internally
generated clamp.
When the external clamp control bit is set to 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync. The clamp place
ment may be programmed to any value up to 255, except 0.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
When the external clamp control bit is set to 1, this register
is ignored.
7-0
An 8-bit register that sets the duration of the internally
generated clamp.
When the external clamp control bit is set to 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync, and continues for
(Clamp Duration) pixel periods. The clamp duration may
Charge Pump Current
Clock Phase Adjust
Clamp Placement
Clamp Duration
VCORNGE
00
01
10
11
Table VII. Charge Pump Currents
CURRENT
000
001
010
011
100
101
110
111
Table VI. VCO Ranges
Pixel Rate Range
10–41
41–82
82–150
150+
Current (mA)
50
100
150
250
350
500
750
1500
REV. B