PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 122

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.5.92
7.5.93
7.5.94
7.5.95
PERICOM SEMICONDUCTOR - Confidential
UPSTREAM MEMORY 0 TRANSLATED BASE - OFFSET E0h
UPSTREAM MEMORY 0 SETUP REGISTER – OFFSET E4h
UPSTREAM I/O OR MEMORY 1 TRANSLATED BASE REGISTER – OFFSET E8h
UPSTREAM I/O OR MEMORY 1 SETUP REGISTER – OFFSET ECh
Bit
11:0
31:12
Bit
0
2:1
3
11:4
30:12
31
Bit
5:0
31:6
Bit
0
Function
Reserved
Downstream
Memory 0
Translated Base
Function
Type Selector
Address Type
Prefetchable Control
Reserved
Base Address
Register Size
Base Address
Register Enable
Function
Reserved
Upstream I/O or
Memory 1
Translated Base
Function
Type Selector
RO (WS)
RO (WS)
RO (WS)
Type
Type
Type
Type
(WS)
RW
RW
RO
RO
RO
RO
RO
RO
Page 122 of 165
Description
Reset to 000h
Define the translated base address for upstream memory transactions whose
initiator addresses fall into Upstream Memory 0 (above lower 4K boundary)
address range. The number of bits that are used for translated base is
determined by its setup register (offset E4h)
Reset to 00000h
Description
0: Memory space is requested
Reset to 0
00: 32-bit address space
01: 64-bit address space
Reset to 00
0: Non-prefetchable
1: Prefetchable
Reset to 0
Reset to 00h
0: Set the corresponding bit in the Base Address Register to read only.
1: Set the corresponding bit in the Base Address Register to read/write in order
to control the size of the address range.
Reset to 00000h
Always set to 1 when a bus master attempts to write a zero to this bit.
PI7C9X130 returns bit [31:12] as FFFFFh (for 4KB size).
Reset to 1
Description
Reset to 000000
Define the translated base address for upstream I/O or memory transactions
whose initiator addresses fall into Upstream I/O or Memory 1 address range.
The number of bits that are used for translated base is determined by its setup
register (offset ECh)
Reset to 00000h
Description
0: Memory space is requested
Reset to 0
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130