PI7C9X130DNDE Pericom Semiconductor, PI7C9X130DNDE Datasheet - Page 137

• Manufacturer Part Number: PI7C9X130DNDE
• Description: IC PCIE-PCIX BRIDGE 1PORT 256BGA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X130DNDE

• Applications: PCI-to-PCI Bridge
• Interface: SMBus (2-Wire/I²C)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 256-PBGA
• Mounting Type: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.6.12
7.6.13
PERICOM SEMICONDUCTOR - Confidential
LOOKUP TABLE DATA – OFFSET 054h
UPSTREAM PAGE BOUNDARY IRQ 0 REQUEST REGISTER - OFFSET 058h
Bit
0
2:1
3
7:4
24:8
31:25
Bit
31:0
Function
Valid
Reserved
Prefetchable
Reserved
Translated base or
Reserved
Translated Base
Function
Upstream Page
Boundary IRQ 0
RW/RO
Type
Type
RWC
RW
RW
RW
RO
RO
Page 137 of 165
Description
0: Invalid lookup
1: Valid lookup
Reset to 0
Reset to 00
0: Memory address is non-prefetchable
1: Memory address is
Reset to 0
Reset to 0h
Data written or read from the Lookup Table at the offset specified in the
Lookup Table Offset Register. When writing to this register, the data value is
written to the specified Lookup Table entry. When reading from this register,
the data reflects the data value from the specified Lookup Table entry. The bit
[24:8] is Translated Base Register bit when the lookup table size is set to 256B
range. The bit [24:8] is reserved when the lookup table size is set to 32MB
range (see PCI configuration offset 68h for non-transparent mode).
Reset to 0
Data written or read from the Lookup Table at the offset specified in the
Lookup Table Offset Register. When writing to this register, the data value is
written to a specific Lookup Table entry (CSR offset 100h – 1FFh). When
reading from this register, the data reflects the data value from the specific
Lookup Table entry.
Reset to 0
Description
Each interrupt request bit is correspondent to a page entry in the lower half of
the Upstream Memory 2 range. Bit [0] is for the first page, and bit [31] is for
the 32
transfers data to or from the imitator that addresses the last Double Word in a
page. PI7C9X130 initiates an interrupt request on secondary interface when
the interrupt request bit is set and the corresponding Upstream Page Boundary
IRQ 0 Mask bit is reset. When forward bridge, PI7C9X130 asserts INTA_L or
generates MSI on secondary bus (PCI interface). When reverse bridge,
PI7C9X130 sends INTA_L assertion message or generates MSI on secondary
interface (PCI Express).
When writing a “1” to this register, it clears the corresponding interrupt request
bit.
Reset to 0
nd
page. PI7C9X130 sets the appropriate bit when it successfully
PCI EXPRESS TO PCI-X BRIDGE
Mar 2010 - Rev 2.0
PI7C9X130